BUS 13 Search Results

MPC821

Contextual Info: SECTION 13 EXTERNAL BUS INTERFACE 13.1 OVERVIEW The MPC821 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC821 architecture supports byte, half-word, and

MPC860

Contextual Info: SECTION 13 EXTERNAL BUS INTERFACE 13.1 OVERVIEW The MPC860 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC860 architecture supports byte, half-word, and

MPC821

Contextual Info: SECTION 13 EXTERNAL BUS INTERFACE 13.1 OVERVIEW The MPC821 bus is a synchronous, burstable bus. Signals driven on this bus are required to make the setup and hold time relative to the bus clock’s rising edge. The bus has the ability to support multiple masters. The MPC821 architecture supports byte, half-word, and

OM5027

Abstract: AN97055 transistor book IC20 Preface the I2c-bus specification 40011
Contextual Info: THE I2C-BUS SPECIFICATION VERSION 2.0 DECEMBER 1998 Philips Semiconductors The I2C-bus specification 13.5.1 F/S-mode transfer in a mixed-speed bus system 13.5.2 Hs-mode transfer in a mixed-speed bus system 13.5.3 Timing requirements for the bridge in a mixed-speed bus system

Contextual Info: LMS75LBC176 LMS75LBC176 Differential Bus Transceivers Literature Number: SNOSA27B LMS75LBC176 October 13, 2011 Differential Bus Transceivers General Description Features The LMS75LBC176 is a differential bus/line transceiver designed for bidirectional data communication on multipoint bus

MPC561

Abstract: MPC563 IMB3
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC566

Abstract: MPC565 NOTES ON MULTIPLEXER
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC555

Abstract: 7f90
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

Contextual Info: LMS75ALS176A LMS75ALS176A Differential Bus Transceivers Literature Number: SNOSA26B LMS75ALS176A October 13, 2011 Differential Bus Transceivers General Description Features The LMS75ALS176A is a differential bus/line transceiver designed for bidirectional data communication on multipoint bus

Motorola MPC555

Abstract: MPC555 MPC556
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC556

Abstract: MPC555 7fa0
Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

MPC555

Contextual Info: SECTION 12 U-BUS TO IMB3 BUS INTERFACE UIMB The U-bus to IMB3 bus interface (UIMB) Interface structure is used to connect the CPU internal unified bus (U-bus) to the intermodule bus 3 (IMB3). It controls bus communication between the U-bus and the IMB3.

VII-320

Abstract: MIL-STD-1553A
Contextual Info: QQ0 ILC DATA DEVICE CORPORATION«_ BUS-69008/09/18/19/23/24/25/28/29II REAL-TIME SOFTWARE FOR THE BUS-6551711 IDEA CARD FEATURES DESCRIPTION These real-time software libraries, the BUS-69008II, BUS-69009II, BUS-6901811, BUS-6901911, BUS-69023, BUS-69024,

UT54ACS164245SEI

Contextual Info: UT54ACS164245SEI RadHard Schmitt CMOS 16-bit Bidirectional MultiPurpose Transceiver Datasheet June 19, 2007 www.aeroflex.com/16BitLogic LOGIC SYMBOL FEATURES • Flexible voltage operation - 5V bus to 3.3V bus; 5V bus to 5V bus - 3.3V bus to 5V bus; 3.3V bus to 3.3V bus

MCF5307

Abstract: MCF5206
Contextual Info: MCF5307 EXTERNAL BUS INTERFACE MCF5307 External Bus Motorola ColdFire 1- 1 MCF5307 EXTERNAL BUS INTERFACE ▼ MCF5307 External Bus Interface – ColdFire® synchronous standard bus interface – 32-bit address bus, 32-bit data bus unmultiplexed – 3-clock basic bus cycle

Contextual Info: HT-1000 I/O CONTROLLER SUMMARY OF BENEFITS FEATURES • The HT-1000 integrates: • 8x HyperTransport bus • Integrated South Bridge • PCI-X 64 bus/133 bus • PCI 32 bus/33 bus • Four-port SATA II • Four-port USB 2.0 • Single-channel ATA 100 IDE

common mode rejection ratio test 1553B

Contextual Info: CT2512 / CT2513 / CT2510 / CT2511 Dual Redundant Remote Terminal FOR MIL-STD-1553B Features CIRCUIT TECHNOLOGY • CT2512 Replaces DDC BUS-65112 and BUS-65117 • CT2513 Replaces DDC BUS-65113 and BUS-65118 • CT2510 Replaces DDC BUS-65110 and BUS-65120 • CT2511 Replaces DDC BUS-65111 and BUS-65121

BUS-65112

Abstract: CT2510 CT2511 CT2512 CT2513 5962-87535
Contextual Info: CT2512 / CT2513 / CT2510 / CT2511 Dual Redundant Remote Terminal FOR MIL-STD-1553B Features CIRCUIT TECHNOLOGY • CT2512 Replaces DDC BUS-65112 and BUS-65117 • CT2513 Replaces DDC BUS-65113 and BUS-65118 • CT2510 Replaces DDC BUS-65110 and BUS-65120 • CT2511 Replaces DDC BUS-65111 and BUS-65121

MPC555

Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC566

Abstract: MPC565
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC555

Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

mpc556

Abstract: MPC555 inl2u
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

MPC555

Abstract: MPC556
Contextual Info: SECTION 11 L-BUS TO U-BUS INTERFACE L2U The L-bus to U-bus interface unit (L2U) provides an interface between the load/store bus (L-bus) and the unified bus (U-bus). The L2U module includes the data memory protection unit (DMPU), which provides protection for data memory accesses.

BUS-65112

Abstract: CT2510 CT2511 CT2512 CT2513 bus-65120
Contextual Info: CT2512 / CT2513 / CT2510 / CT2511 Dual Redundant Remote Terminal FOR MIL-STD-1553B Features CIRCUIT TECHNOLOGY • CT2512 Replaces DDC BUS-65112 and BUS-65117 • CT2513 Replaces DDC BUS-65113 and BUS-65118 • CT2510 Replaces DDC BUS-65110 and BUS-65120 • CT2511 Replaces DDC BUS-65111 and BUS-65121