BUFFER REGISTER Search Results

Contextual Info: Write Buffer WB 7.0 Write Buffer (WB) The ARM710 write buffer is provided to improve system performance. It can buffer up to 8 words of data, and 4 independent addresses. It may be enabled or disabled via the W bit (bit 3) in the ARM710 Control Register and the buffer is disabled and flushed on reset. The operation of the write buffer is further

Contextual Info: ZLAN-47 Applications of the ZL50400/4/5/7/8/9/10/11 Buffer Allocation Application Note Contents December 2004 1.0 Introduction 2.0 Available Buffer Allocation 3.0 Register Settings 3.1 Buffer Reservation Registers 3.2 Buffer Threshold Registers 3.3 BUF_LIMIT

Contextual Info: PSoC Creator Component Datasheet Tri-State Buffer Bufoe 1.10 Features • Buffer with Output Enable signal • Feedback signal General Description The Tri-State Buffer (Bufoe) component is a non-inverting buffer with an active high output enable signal. When the output enable signal is true, the buffer functions as a standard buffer.

74ABT541

Abstract: 74ABT245 74ABT273 74ABT373 74ABT374 74ABT377 74ABT125 74ABT126 74ABT240 74ABT241
Contextual Info: Logic Products by Family ABT Products Logic Product Function Product Description Package Voltage Node 74ABT125 Buffer Quad Buffer with 3-STATE Outputs SOIC SOP TSSOP 5 74ABT126 Buffer Quad Buffer with 3-STATE Outputs SOIC SOP TSSOP 5 74ABT240 Buffer, Line Driver

Contextual Info: ZLAN-145 MVTX280x Buffer Allocation Application Note Contents April 2005 The available buffers for configuration are calculated in the following formula: 1.0 Introduction 2.0 Available Buffer Allocation 3.0 Register Settings 3.1 Buffer Reservation and Threshold Registers

Contextual Info: IDT74SSTUA32866 1.8V CONFIGURABLE REGISTERED BUFFER WITH ADDRESS-PARITY TEST 1.8V CONFIGURABLE BUFFER WITH ADDRESSPARITY TEST 1.8V Operation SSTL_18 style clock and data inputs Differential CLK input Configurable as 25-bit 1:1 or 14-bit 1:2 registered buffer

Contextual Info: Figure 1. Block Diagram F l F l F I F I F ] □ _ Clock Doubler/ Ttoo-Phase Generator PHASE-LOCKED CONTROL LOGIC LOOP P IL \ MUX DIVIDE "0 OUTPUT BUFFER OUTPUT BUFFER OUTPUT BUFFER LlJ Li] /— Oata Sheets F l GA1210E LOGIC OUTPUT BUFFER lD OUTPUT BUFFER

Contextual Info: ZLAN-7 MVTX260x/ZL5041x Buffer Allocation Application Note Contents 1.0 Introduction 2.0 Available Buffer Allocation 3.0 QoS Buffer Allocation 1.0 Introduction This application note illustrates an example on the buffer allocation for the MVTX260x/ZL5041x Ethernet

Contextual Info: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 14-BIT REGISTERED BUFFER WITH SSTL I/O IDT74SSTVF16857 FEATURES: DESCRIPTION: • • • • • • • • The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V

Contextual Info: IDT74SSTU32865 28-BIT 1:2 REGISTERED BUFFER WITH PARITY COMMERCIAL TEMPERATURE RANGE 28-BIT 1:2 REGISTERED BUFFER WITH PARITY IDT74SSTU32865 FEATURES: DESCRIPTION: • • • • • • • The SSTU32865 is a 28-bit 1:2 configurable registered buffer designed

Contextual Info: IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE IDT74SSTVF16857 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • The SSTVF16857 is a 14-bit registered buffer designed for 2.3V-2.7V

mm54

Abstract: MM54HC365 MM54HC366 MM54HC367 MM54HC368 74HC367 MM74HC365 MM74HC366 MM74HC367 MM74HC368
Contextual Info: MM54HC365 MM54HC366 MM54HC367 MM54HC368 MM74HC365 Hex TRI-STATE Buffer MM74HC366 Inverting Hex TRI-STATE Buffer MM74HC367 Hex TRI-STATE Buffer MM74HC368 Inverting Hex TRI-STATE Buffer General Description These TRI-STATE buffers are general purpose high speed

MM54HC366

Abstract: MM54HC368 MM54HC365
Contextual Info: MM54HC365/MM74HC365 MM54HC366/MM74HC366 MM54HC367/MM74HC367 MM54HC368/MM74HC368 Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer General Description These TRI-STATE buffers are general purpose high speed

Contextual Info: PRELIMINARY Precision 1-18 Clock Buffer Features Description • High speed, low noise non-inverting 1-18 buffer The PI6C180 is a high-speed low-noise 1-18 non-inverting buffer designed for SDRAM clock buffer applications.

MM54HC366

Abstract: MM54HC368 MM54HC365 MM54HC367
Contextual Info: January 1988 Semiconductor & MM54HC365/MM74HC365 MM54HC366/MM74HC366 MM54HC367/MM74HC367 MM54HC368/MM74HC368 Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer General Description These TRI-STATE buffers are general purpose high speed

Contextual Info: CY2313ANZ 13 Output, 3.3 V Clock Buffer 13 Output, 3.3 V Clock Buffer Features Functional Description • One input to 13 output buffer/driver The CY2313ANZ is a 3.3 V clock buffer. While originally designed to distribute clocks in desktop PC applications - hence

Contextual Info: IDT74SSTVM16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED IDT74SSTVM16859 BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 1:2 register buffer Meets or exceeds JEDEC standard SSTVM16859

SO48-2

Abstract: SSTV16857
Contextual Info: IDT74SSTV16857 14-BIT REGISTERED BUFFER WITH SSTL I/O INDUSTRIAL TEMPERATURE RANGE IDT74SSTV16857 ADVANCE INFORMATION 14-BIT REGISTERED BUFFER WITH SSTL I/O FEATURES: – – – – – – – – – DESCRIPTION: The SSTV16857 is a 14-Bit registered buffer designed for 2.3V-2.7V

Contextual Info: A ugust 1998 54AC241 • 54ACT241 Octal Buffer/Line Driver with TRI-STATE Outputs General Description N on-inverting TR I-STATE outputs drive bus lines or buffer m em ory address registers The ’A C /’ACT241 is an octal buffer and line d river designed

MM74HC367N

Abstract: 74HC367 5209-1 MM74HC367M 54HC368 MM74HC365M MM54HC366 MM54HC368 MM54HC365
Contextual Info: January 1988 Semiconductor & MM54HC365/MM74HC365 MM54HC366/MM74HC366 MM54HC367/MM74HC367 MM54HC368/MM74HC368 Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer Hex TRI-STATE Buffer Inverting Hex TRI-STATE Buffer General Description These TR I-STATE b uffers are general purpose high speed

Contextual Info: IDT74SSTVM16859 13-BIT TO 26-BIT REGISTERED BUFFER WITH SSTL I/O COMMERCIAL TEMPERATURE RANGE 13-BIT TO 26-BIT REGISTERED IDT74SSTVM16859 BUFFER WITH SSTL I/O FEATURES: DESCRIPTION: • • • • • • • • 1:2 register buffer Meets or exceeds JEDEC standard SSTVM16859

CY2313ANZ

Abstract: milli farad capacitor 121-831 CY2313ANZSC-1
Contextual Info: CY2313ANZ 13 Output, 3.3 V Clock Buffer 13 Output, 3.3 V Clock Buffer Features Functional Description • One input to 13 output buffer/driver The CY2313ANZ is a 3.3 V clock buffer. While originally designed to distribute clocks in desktop PC applications - hence

Contextual Info: PI6C182 PI6C182A Precision 1-to-10 Clock Buffer Features Description • Low noise non-inverting 1-to-10 buffer The PI6C182 is a high-speed low-noise 1-to-10 noninverting buffer designed for SDRAM clock buffer applications, supporting frequencies up to 110 MHz.

Contextual Info: PRELIMINARY Precision 1-13 Clock Buffer Features Description • High speed, low noise non-inverting 1-13 buffer The PMC 184 is a high-speed low-noise 1-13 non-inverting buffer designed for SDRAM clock buffer applications. • Supports up to four SDRAM DIMMs