BROADBAND TIME DELAY Search Results

Contextual Info: HMC877LC3 v03.0413 BROADBAND TIME DELAY & PHASE SHIFTER SMT, 8 - 23 GHz Typical Applications Features The HMC877LC3 is ideal for: Very Wide Bandwidth: 8 - 23 GHz • Synchronization of clock and data Continuous Adjustable Delay Range: 500° 1.4 UI[1] • Transponder design

STM-256

Abstract: 43Gb EA Modulator Driver
Contextual Info: CENTELLAX OA4SMME Datasheet 43Gb/s Broadband Electroabsorption Modulator Driver Amplifier Product Highlights • 3.3Vp-p output swing • 0.6ps added RMS jitter • 8ps rise / fall time • 17dB gain to 45GHz • 16dBm saturated output power • 1.2W power dissipation

Contextual Info: broadband, linear Pulse Amplifiers up to 200 mW 23 dBm output inverting or non-inverting case style selection outline draw ings see Table o f Contents ZPUL FREQ. MHz GAIN, dB RISE/FALL PULSE POLARITY MAXIMUM DYNAMIC TIME WIDTH* POWER, dBm RANGE MODEL NO.

Contextual Info: CENTELLAX OA3MVM2 Datasheet OA3MVM2 30 Gb/s Broadband Driver Amplifier Product Highlights • 8Vp-p 23 dBm saturated output power • < 8 ps rise/fall time • <0.5 ps added rms jitter • 30 dB gain • 3.4 W Power Dissipation • Small Size Package Description

Contextual Info: CD74ACT158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCHS341 – MARCH 2003 D D D D D D M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays

DIL-16

Abstract: SOIC-16 UC1708 UC2708 UC3708 UDG-92025
Contextual Info: application INFO available UC1708 UC2708 UC3708 Dual Non-Inverting Power Driver FEATURES • 3.0A Peak Current Totem Pole Output • 5 to 35V Operation • 25ns Rise and Fall Times • 25ns Propagation Delays • Thermal Shutdown and UnderVoltage Protection

Contextual Info: CD54ACT153, CD74ACT153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCHS339 – MARCH 2003 D D D D D D Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current

Contextual Info: UC1711 UC3711 Dual Ultra High-Speed FET Driver FEATURES BLOCK DIAGRAM • 25ns Rise and Fall into 1000pF • 15ns Propagation Delay 7.5V REG • 1.5A Source or Sink Output Drive 6 VCC 7 A Out 5 B Out 3 Gnd 3k • Operation with 5V to 35V Supply 2.5k • High-Speed Schottky NPN Process

BFU790F

Contextual Info: AN11114 2.4-5.9GHz Broadband WiFi LNA With BFU730F Rev. 1 — 26 October 2012 Application note Document information Info Content Keywords BFU730F, Broadband LNA, WiFi WLAN Abstract This document provides circuit simulation, schematic, layout, BOM and typical EVB performance for a broadband WiFi (WLAN) LNA

CD74HCU04

Abstract: CD74HCU04E CD74HCU04M CD74HCU04M96 CD74HCU04MT CD74HCU04PWR HCU04 MTSS001C
Contextual Info: [ /Title CD74 HCU04 /Subject (High Speed CMOS Logic Hex Inverter CD74HCU04 Data sheet acquired from Harris Semiconductor SCHS127D High-Speed CMOS Logic Hex Inverter February 1998 - Revised May 2004 Features Description • Typical Propagation Delay: 6ns at VCC = 5V,

CD74ACT158

Abstract: CD74ACT158M96
Contextual Info: CD74ACT158 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCHS341 – MARCH 2003 D D D D D D M PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays

Contextual Info: SN74AS1804 HEX 2-INPUT NAND DRIVER SDAS042C – AUGUST 1984 – REVISED JANUARY 1995 • • DW OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 9 mW Per Gate Center VCC and GND Configuration

Contextual Info: SN74AS1832 HEX 2-INPUT OR DRIVER SDAS045C – AUGUST 1984 – REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: UC1711 UC3711 Dual Ultra High-Speed FET Driver FEATURES BLOCK DIAGRAM • 25ns Rise and Fall into 1000pF • 15ns Propagation Delay 7.5V REG • 1.5A Source or Sink Output Drive 6 VCC 7 A Out 5 B Out 3 Gnd 3k • Operation with 5V to 35V Supply 2.5k • High-Speed Schottky NPN Process

Contextual Info: UC1711 UC3711 Dual Ultra High-Speed FET Driver FEATURES BLOCK DIAGRAM • 25ns Rise and Fall into 1000pF • 15ns Propagation Delay 7.5V REG • 1.5A Source or Sink Output Drive 6 VCC 7 A Out 5 B Out 3 Gnd 3k • Operation with 5V to 35V Supply 2.5k • High-Speed Schottky NPN Process

CD54ACT153

Abstract: CD54ACT153F3A CD74ACT153 CD74ACT153E CD74ACT153M CD74ACT153M96 act153m
Contextual Info: CD54ACT153, CD74ACT153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCHS339 – MARCH 2003 D D D D D D Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current

CDC204

Abstract: CDC204DW CDC204DWR CDC204DWRG4 CDC204N MS-013
Contextual Info: CDC204 HEX INVERTER/CLOCK DRIVER SCAS098E – OCTOBER 1989– REVISED OCTOBER 1998 D D D D D D D D DW PACKAGE TOP VIEW CDC204 Replaces 74AC11204 Low-Skew Propagation Delay Specifications for Clock-Driver Applications CMOS-Compatible Inputs and Outputs Flow-Through Architecture Optimizes

Contextual Info: CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCHS316 – NOVEMBER 2002 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With D D D D E OR M PACKAGE TOP VIEW Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current

CD74ACT10

Abstract: CD74ACT10E CD74ACT10EE4 CD74ACT10M CD74ACT10M96 CD74ACT10M96E4
Contextual Info: CD74ACT10 TRIPLE 3-INPUT POSITIVE-NAND GATES SCHS316 – NOVEMBER 2002 D Inputs Are TTL-Voltage Compatible D Speed of Bipolar F, AS, and S, With D D D D E OR M PACKAGE TOP VIEW Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current

Contextual Info: CD74HC08ĆEP QUADRUPLE 2ĆINPUT POSITIVEĆAND GATES SCLS477B − APRIL 2003 − REVISED APRIL 2004 D Controlled Baseline D D D D D D D D Balanced Propagation Delay and Transition − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of Up

Contextual Info: AM26S10C QUADRUPLE BUS TRANSCEIVERS SLLS116C – JANUARY 1977 – REVISED MARCH 1997 D D D D D D OR N PACKAGE TOP VIEW Schottky Circuitry for High Speed, Typical Propagation Delay Time . . . 12 ns Drivers Feature Open-Collector Outputs for Party-Line (Data Bus) Operation

SN74AS1805

Contextual Info: SN74AS1805 HEX 2ĆINPUT NOR DRIVER ą SDAS043C − AUGUST 1984 − REVISED JANUARY 1995 • • DW OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 2.6 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 12 mW Per Gate

Contextual Info: SN74AS1832 HEX 2ĆINPUT OR DRIVER ą SDAS045C − AUGUST 1984 − REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: SN74AS1808 HEX 2ĆINPUT AND DRIVER ą SDAS044C − AUGUST 1984 − REVISED JANUARY 1995 • • N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.2 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 13 mW Per Gate Center VCC and GND Configuration