BROADBAND TIME DELAY Search Results

Contextual Info: CD54ACT153, CD74ACT153 DUAL 4-LINE TO 1-LINE DATA SELECTORS/MULTIPLEXERS SCHS339 – MARCH 2003 D D D D D D Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays ±24-mA Output Drive Current

Contextual Info: UC1711 UC3711 Dual Ultra High-Speed FET Driver FEATURES BLOCK DIAGRAM • 25ns Rise and Fall into 1000pF • 15ns Propagation Delay 7.5V REG • 1.5A Source or Sink Output Drive 6 VCC 7 A Out 5 B Out 3 Gnd 3k • Operation with 5V to 35V Supply 2.5k • High-Speed Schottky NPN Process

Contextual Info: SN74AS1832 HEX 2-INPUT OR DRIVER SDAS045C – AUGUST 1984 – REVISED JANUARY 1995 • • D OR N PACKAGE TOP VIEW High Capacitive-Drive Capability Typical Delay Time of 3.9 ns (CL = 50 pF) and Typical Power Dissipation of Less Than 17 mW per Gate Center VCC and GND Configuration

Contextual Info: AM26S10C QUADRUPLE BUS TRANSCEIVERS SLLS116C – JANUARY 1977 – REVISED MARCH 1997 D D D D D D OR N PACKAGE TOP VIEW Schottky Circuitry for High Speed, Typical Propagation Delay Time . . . 12 ns Drivers Feature Open-Collector Outputs for Party-Line (Data Bus) Operation

Contextual Info: CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30%

CD74ACT157

Abstract: CD74ACT157E CD74ACT157M CD74ACT157M96 CD74ACT157PW CD74ACT157PWR hm157
Contextual Info: CD74ACT157 QUADRUPLE 2-LINE TO 1-LINE DATA SELECTOR/MULTIPLEXER SCHS340B – MARCH 2003 - REVISED JUNE 2003 D D D D D D Inputs Are TTL-Voltage Compatible Speed of Bipolar F, AS, and S, With Significantly Reduced Power Consumption Balanced Propagation Delays

Contextual Info: [ /Title CD74 HCU04 /Subject (High Speed CMOS Logic Hex Inverter CD74HCU04 Data sheet acquired from Harris Semiconductor SCHS127D High-Speed CMOS Logic Hex Inverter February 1998 - Revised May 2004 Features Description • Typical Propagation Delay: 6ns at VCC = 5V,

Contextual Info: UC1824 UC2824 UC3824 High Speed PWM Controller FEATURES DESCRIPTION • Complementary Outputs • Practical Operation Switching Frequencies to 1MHz • 50ns Propagation Delay to Output • High Current Dual Totem Pole Outputs 1.5A Peak The UC1824 family of PWM control ICs is optimized for high frequency switched mode power supply applications. Particular care

Contextual Info: CD54HC4017 DECADE COUNTER/DIVIDER WITH TEN DECODED OUTPUTS SGDS011 – MAY 1999 D D D D D D D D 2-V to 6-V Operation Fully Static Operation Buffered Inputs Common Reset Positive-Edge Clocking Balanced Propagation Delay and Transition Times High Noise Immunity: NIL = 30%, NIH = 30%

Contextual Info: CD74HCT574ĆEP HIGHĆSPEED CMOS LOGIC OCTAL DĆTYPE FLIPĆFLOP 3ĆSTATE, POSITIVEĆEDGE TRIGGERED SCLS571 − FEBRUARY 2004 D Controlled Baseline D D D D D D D D D D D Balanced Propagation Delay and Transition − One Assembly/Test Site, One Fabrication Site

Contextual Info: UC2856Q www.ti.com SGLS265 – NOVEMBER 2004 IMPROVED CURRENT MODE PWM CONTROLLER FEATURES • • • • • • • • • DW PACKAGE TOP VIEW Pin-for-Pin Compatible With the UC2846 65-ns Typical Delay From Shutdown to Outputs and 50-ns Typical Delay From

Contextual Info: UC1543 UC1544 UC2543 UC2544 UC3543 UC3544 Power Supply Supervisory Circuit FEATURES • Includes Over-voltage, Under-voltage, And Current Sensing Circuits • Internal 1% Accurate Reference • Programmable Time Delays • SCR “Crowbar” Drive Of 300mA

UCC5686

Abstract: UCC5686PM UCC5686PMTR UCC5687 UCC5687PM ULTRA160 ULTRA320
Contextual Info: UCC5686, UCC5687 27-LINE 3ĆV - 5ĆV LVD TERMINATOR FOR WIDE ULTRA2, ULTRA3, ULTRA160, AND ULTRA320 SCSI WITH INTEGRATED SPIĆ3 DELAY ą SLUS459B – OCTOBER 2000 – REVISED APRIL 2001 D SCSI SPI-2, SPI-3, Ultra2, Ultra3, Ultra160, D D D D REG SGND PGND LVD

Contextual Info: CD74HC40103ĆEP HIGHĆSPEED CMOS LOGIC 8ĆSTAGE SYNCHRONOUS DOWN COUNTER SCLS548 − DECEMBER 2003 D Controlled Baseline D D D D D D D D Balanced Propagation Delay and Transition − One Assembly/Test Site, One Fabrication Site Extended Temperature Performance of

Contextual Info: application INFO available UC1708 UC2708 UC3708 Dual Non-Inverting Power Driver FEATURES • 3.0A Peak Current Totem Pole Output • 5 to 35V Operation • 25ns Rise and Fall Times • 25ns Propagation Delays • Thermal Shutdown and UnderVoltage Protection

Contextual Info: CDC208 DUAL 1-LINE TO 4-LINE CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS109F – APRIL 1990 – REVISED OCTOBER 1998 D D D D D D D DW PACKAGE TOP VIEW Low-Skew Propagation Delay Specifications for Clock-Driver Applications TTL-Compatible Inputs and CMOS-Compatible Outputs

Contextual Info: SN54ALS805A, SN54AS805B, SN74ALS805A, SN74AS805B HEX 2-INPUT NOR DRIVERS SDAS023C – DECEMBER 1982 – REVISED JANUARY 1995 SN54ALS805A, SN54AS805B . . . J PACKAGE SN74ALS805A, SN74AS805B . . . DW OR N PACKAGE TOP VIEW High Capacitive-Drive Capability ′ALS805A Has Typical Delay Time of 4.2 ns

Contextual Info: UC1856 UC2856 UC3856 Improved Current Mode PWM Controller FEATURES DESCRIPTION • Pin-for-Pin Compatible With the UC3846 • 65ns Typical Delay From Shutdown to Outputs, and 50ns Typical Delay From Sync to Outputs • Improved Current Sense Amplifier With

Contextual Info: CD74HC4538ĆQ1 HIGHĆSPEED CMOS LOGIC DUAL RETRIGGERABLE PRECISION MONOSTABLE MULTIVIBRATOR SCLS595 − NOVEMBER 2004 D Qualification in Accordance With D D D D D D D D D D D D Balanced Propagation Delay and Transition AEC-Q100† Qualified for Automotive Applications

Contextual Info: [ /Title CD74 HCU04 /Subject (High Speed CMOS Logic Hex Inverter CD74HCU04 Data sheet acquired from Harris Semiconductor SCHS127D High-Speed CMOS Logic Hex Inverter February 1998 - Revised May 2004 Features Description • Typical Propagation Delay: 6ns at VCC = 5V,

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Contextual Info: Positioning Paper Broadband Acceleration The Economic Benefits of Caching Broadband acceleration—the use of intelligent caching techniques to store content closer to end users—can provide significant economic benefits to access service providers. About This Document

Contextual Info: SN65LBC174A, SN75LBC174A QUADRUPLE RSĆ485 DIFFERENTIAL LINE DRIVERS SLLS446C − OCTOBER 2000 − REVISED MAY 2003 D Designed for TIA/EIA-485, TIA/EIA-422 and D Driver Positive- and Negative-Current ISO 8482 Applications Signaling Rates† up to 30 Mbps Propagation Delay Times < 11 ns

Contextual Info: SN65LBC174A, SN75LBC174A QUADRUPLE RSĆ485 DIFFERENTIAL LINE DRIVERS SLLS446C − OCTOBER 2000 − REVISED MAY 2003 D Designed for TIA/EIA-485, TIA/EIA-422 and D Driver Positive- and Negative-Current ISO 8482 Applications Signaling Rates† up to 30 Mbps Propagation Delay Times < 11 ns

Contextual Info: SN65LBC174A, SN75LBC174A QUADRUPLE RSĆ485 DIFFERENTIAL LINE DRIVERS SLLS446C − OCTOBER 2000 − REVISED MAY 2003 D Designed for TIA/EIA-485, TIA/EIA-422 and D Driver Positive- and Negative-Current ISO 8482 Applications Signaling Rates† up to 30 Mbps Propagation Delay Times < 11 ns