BC4 BL4 BL8 OTF Search Results

Contextual Info: DATA SHEET 1G bits DDR3 SDRAM EDJ1108DBSE 128M words x 8 bits EDJ1116DBSE (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization ⎯ 16M words × 8 bits × 8 banks (EDJ1108DBSE) ⎯ 8M words × 16 bits × 8 banks (EDJ1116DBSE)

EDJ1108DJBG-DJ-F

Contextual Info: DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG 128M words x 8 bits EDJ1116DJBG (64M words × 16 bits) • Density: 1G bits • Organization 16M words × 8 bits × 8 banks (EDJ1108DJBG) 8M words × 16 bits × 8 banks (EDJ1116DJBG) • Package 78-ball FBGA (EDJ1108DJBG)

hynix ddr3

Abstract: bc4 bl4 bl8 otf ddr3 2133 diode T9 AC-DC DDR3-1333 DDR3-1866 DDR3-2133 a12b DD3-800
Contextual Info: APCPCWM_4828539:WP_0000002WP_000000 APCPCWM_4828539:WP_0000002WP_0000002 DDR3+ Device Operation DDR3+ SDRAM Device Operation 1 *3e46a6cd-6391* B20337/178.104.2.234/2010-08-27 12:03 APCPCWM_4828539:WP_0000002WP_000000 APCPCWM_4828539:WP_0000002WP_0000002 DDR3+ Device Operation

bc4 bl4 bl8 otf

Abstract: 240 pin DIMM DDR3 through hole
Contextual Info: DDR3 Device Operation DDR3 SDRAM Device Operation 1 DDR3 Device Operation Contents 1. Functional Description 1.1 Simplified State Diagram 1.2 Basic Functionality 1.3 RESET and Initialization Procedure 1.3.1 Power-up Initialization Sequence 1.3.2 Reset Initialization with Stable Power

ELPIDA DDR3

Contextual Info: PRELIMINARY DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG 128M words x 8 bits EDJ1116DJBG (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (EDJ1108DJBG)  8M words × 16 bits × 8 banks (EDJ1116DJBG)

ELPIDA DDR3

Abstract: ELPIDA DRAM selection guide ELPIDA DDR3 User
Contextual Info: DATA SHEET 1G bits DDR3 SDRAM EDJ1108DJBG 128M words x 8 bits EDJ1116DJBG (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (EDJ1108DJBG)  8M words × 16 bits × 8 banks (EDJ1116DJBG)

EDJ1108DBSE

Abstract: EDJ1116DBSE-DJ-F EDJ1108DBSE-GN-F EDJ1116DBSE EDJ1108DBSE-DJ-F EDJ1116DBSE-GN-F ELPIDA DDR3 EDJ1108 EDJ1116DBSE-DJ 78-Ball
Contextual Info: DATA SHEET 1G bits DDR3 SDRAM EDJ1108DBSE 128M words x 8 bits EDJ1116DBSE (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization  16M words × 8 bits × 8 banks (EDJ1108DBSE)  8M words × 16 bits × 8 banks (EDJ1116DBSE)

ELPIDA DDR3

Abstract: EDJ2116DEBG-DJ-F EDJ2108DEBG-GN bc4 bt ELPIDA DDR3 2G ELPIDA DDR3 User
Contextual Info: PRELIMINARY DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG 256M words x 8 bits EDJ2116DEBG (128M words × 16 bits) Specifications Features • Density: 2G bits • Organization:  32M words × 8 bits × 8 banks (EDJ2108DEBG)  16M words × 16 bits × 8 banks (EDJ2116DEBG)

EDJ2116DEBG-DJ-F

Abstract: edj2116debg EDJ2116DEBG-GN-F ELPIDA DDR3 EDJ2108DEBG ELPIDA DDR3 2G
Contextual Info: PRELIMINARY DATA SHEET 2G bits DDR3 SDRAM EDJ2108DEBG 256M words x 8 bits EDJ2116DEBG (128M words × 16 bits) Specifications Features • Density: 2G bits • Organization:  32M words × 8 bits × 8 banks (EDJ2108DEBG)  16M words × 16 bits × 8 banks (EDJ2116DEBG)

Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR3 SDRAM EDJ5316DBBG 32M words x 16 bits Specifications Features • Density: 512M bits • Organization: 4M words × 16 bits × 8 banks • Package: 96-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V

EDJ1108DBSE

Contextual Info: PRELIMINARY DATA SHEET 1G bits DDR3 SDRAM EDJ1108DBSE 128M words x 8 bits EDJ1116DBSE (64M words × 16 bits) Specifications Features • Density: 1G bits • Organization ⎯ 16M words × 8 bits × 8 banks (EDJ1108DBSE) ⎯ 8M words × 16 bits × 8 banks (EDJ1116DBSE)

ELPIDA DDR3

Abstract: DDR3 jedec
Contextual Info: PRELIMINARY DATA SHEET 512M bits DDR3 SDRAM EDJ5316DBBG 32M words x 16 bits Specifications Features • Density: 512M bits • Organization: 4M words × 16 bits × 8 banks • Package: 96-ball FBGA  Lead-free (RoHS compliant) and Halogen-free • Power supply: VDD, VDDQ = 1.5V ± 0.075V

bc4 bl4 bl8 otf

Abstract: srt 8n TI ddr3 controller "DDR3 SDRAM" TI ddr3 controller datasheet T145
Contextual Info: DDR3 SDRAM Device Operation DDR3 SDRAM DDR3 SDRAM Specification Device Operation & Timing Diagram February 2009 revision 0.63 INFORMATION IN THIS DOCUMENT IS PROVIDED IN RELATION TO SAMSUNG PRODUCTS, AND IS SUBJECT TO CHANGE WITHOUT NOTICE. NOTHING IN THIS DOCUMENT SHALL BE

Contextual Info: AS4C256M16D3 Revision History AS4C256M16D3 - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amended temperature range to Table 2. Ordering Information - page 1 - Commercial Extended (0 ~ 95°C) - Industrial (-40 ~ 95°C) Date

Contextual Info: AS4C128M16D3 2Gb 128M x 16 bit DDR3 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.0, Feb. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.5V  0.075V  Operating temperature: - Commercial (0 ~ 95°C)

Contextual Info: AS4C256M8D3 Revision History AS4C256M8D3 - 78-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Amended temperature range to Table 2. Ordering Information - page 1 - Commercial Extended (0 ~ 95°C)- Industrial (-40 ~ 95°C) Date February 2014

Contextual Info: AS4C128M16D3 REVISION HISTORY Revision Rev. 1.0 Rev. 2.0 Confidential Description Initial Issue Typing error – in Table 2 page 2 – incorrect temperature range amended to: - Commercial 0 ~ 95°C - Industrial (-40 ~ 95°C) 1 Rev. 2.0 Issue Date February 2014

Contextual Info: 2Gb DDR3L – AS4C256M8D3L 256M x 8 bit DDR3L Synchronous DRAM SDRAM Confidential Advanced (Rev. 1.0, April. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.35V  Backward compatible to VDD & VDDQ = 1.5V ±0.075V

AS4C256M16D3

Contextual Info: AS4C256M16D3 Revision History AS4C256M16D3 - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Rev 3.0 Details Preliminary datasheet Typo in Table 2 – incorrect part no. page 2 Updated Table 11. Recommended DC Operating Conditions – page 21 Added CL=5 & CL=6 to Table 18 – page 26

Contextual Info: AS4C256M8D3 2 Gb 256M x 8 bit DDR3 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.0, Feb. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.5V  0.075V  Operating temperature: - Commercial (0 ~ 95°C)

Contextual Info: AS4C512M8D3 4Gb 512M x 8 bit DDR3 Synchronous DRAM (SDRAM) Confidential Advanced (Rev. 1.0, Feb. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = +1.5V  0.075V  Operating temperature: - Commercial (0 ~ 95°C) - Industrial (-40 ~ 95°C)

Contextual Info: 2Gb DDR3L – AS4C128M16D3L 128M x 16 bit DDR3L Synchronous DRAM SDRAM Confidential Advanced (Rev. 1.0, April. /2014) Features Overview • JEDEC Standard Compliant  Power supplies: VDD & VDDQ = 1.35V  Backward compatible to VDD & VDDQ = 1.5V ±0.075V

AS4C128M16D3L

Contextual Info: 2Gb DDR3L – AS4C128M16D3L Revision History AS4C128M16D3L - 96-ball FBGA PACKAGE Revision Rev 1.0 Rev 2.0 Details Preliminary datasheet Added "Backward compatible to VDD & VDDQ = 1.5V +/0.075V" - page 2 Updated Table 12. Recommended DC Operating Conditions – page 21

AS4C128M16D3

Contextual Info: AS4C128M16D3 REVISION HISTORY AS4C128M16D3 – 96-ball FBGA PACKAGE Revision Rev. 1.0 Rev. 2.0 Rev 3.0 Confidential Description Initial Issue Typing error – in Table 2 page 2 – incorrect temperature range amended to: - Commercial Extended (0 ~ 95°C)