BA PART II DATE SHEET Search Results

A8RN

Abstract: uPD4502161 D4502161
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT ju P D 4 5 0 2 1 6 1 2M-bit Synchronous DRAM Description The /¿PD4502161 is a high-speed 2,097,152-bit synchronous dynamic random-access memory, organized as 65,536 x 16 x 2 word x bit x bank , respectively. The synchronous DRAM achieves high-speed data transfer using the pipeline architecture.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT P D 4 5 1 2 8 4 4 1 - A 7 5 ,4 5 1 2 8 8 4 1 -A 7 5 , 4 5 1 2 8 1 6 3 -A 7 5 128M-bit Synchronous DRAM, 133MHz 4-bank, LVTTL Description The ,uPD45128441-A75, 45128841-A75 and 45128163-A75 are high-speed 134,217,728-bit synchronous dynamic

Contextual Info: 13 12 10 <L NOTES: 1. MATERIALS HOUSING: 30 X GLASS-FILLED PBT. UL94 V -0 TERMINAL: BRASS 0.60REF. THICK PLATING: OPTIONAL SEE CHARTS SHEETS 2-9 5Hn TIN OVER 2.5Hn NICKEL ALLOVER SELECTIVE SILVER 2Mn MIN SILVER 3-5Mn TIN OVER 2.5Mn NICKEL ALLOVER 2. PRODUCT CONFORMS TO SPECIFICATION P S -9 9020-00 38/39

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT /¿ P D 4 5 6 4 4 4 1 -A 7 5 , 4 5 6 4 8 4 1 -A 7 5 64M-bit Synchronous DRAM, 133MHz 4-bank, LVTTL Description The ,uPD4564441-A75, 4564841-A75 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4 and 2,097,152 x 8 x 4 word x bit x bank , respectively.

Contextual Info: DATA SHEET NEC MOS INTEGRATED CIRCUIT ;iP D 4 5 6 4 4 4 1 , 4 5 6 4 8 4 1 , 4 5 6 4 1 6 3 64M-bit Synchronous DRAM 4-bank, LVTTL Description The ,uPD4564441, 4564841, 4564163 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4, 2,097,152 x 8 x 4, 1,048,576 x16 x 4 word x bit x bank , respectively.

EDD2516AMTA-6B-E

Abstract: auto-10
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516AMTA-6B-E 16M words x 16 bits Description Pin Configurations The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for

AX12

Abstract: DDR400 DDR400B BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5B-E 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508AMTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

AX12

Abstract: DDR400 DDR400B BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5B-E 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508AMTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

EDD2516AMTA-6B-E

Abstract: BT122
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516AMTA-6B-E 16M words x 16 bits Description Pin Configurations The EDD2516AMTA is 256M bits Double Data Rate (DDR) SDRAM organized as 4,194,304 words × 16 bits × 4 banks. Read and write operations are performed at the cross points of the CK and the /CK. This highspeed data transfer is realized by the 2 bits prefetchpipelined architecture. Data strobe (DQS) both for

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT /¿PD4564323 for Rev. E 64M-bit Synchronous DRAM 4-bank, LVTTL Description The ,uPD4564323 is a high-speed 67,108,864-bit synchronous dynamic random -access memory, organized as 524,288 words x 32 bits x 4banks. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

M12939EJ3V0DS00

Abstract: uPD4516421AG5-A10B-9NF uPD4516821AG5-A10-9NF uPD4516161AG5-A10B-9NF 4516161a PD4516821
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421A, 4516821A, 4516161A for Rev.P 16M-bit Synchronous DRAM 2-banks, LVTTL 2 Description The µPD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access memories, organized as 2,097,152 x 4 × 2, 1,048,576 × 8 × 2, 524,288 × 16 × 2 (word × bit × bank , respectively.

DDR400

Abstract: BT122
Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5 32M words x 8 bits, DDR400 EDD2516AMTA-5 (16M words × 16 bits, DDR400) Pin Configurations The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AMTA-5 is a 256M bits

BT122

Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2516ARTA-6B 16M words x 16 bits Specifications Pin Configurations • Density: 256M bits • Organization  4M words × 16 bits × 4 banks • Package: 66-pin plastic TSOP (II) • Power supply: VDD, VDDQ = 2.5V ± 0.2V

AX12

Abstract: DDR400 DDR400B
Contextual Info: DATA SHEET 256M bits DDR SDRAM EDD2508ARTA-5B 32M words x 8 bits, DDR400 Description Pin Configurations The EDD2508ARTA is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. Read and write operations are performed at

BT122

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA 32M words x 8 bits EDD2516AMTA (16M words × 16 bits) Pin Configurations The EDD2508AM is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AM is a 256M bits DDR

DDR400

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA-5 32M words x 8 bits, DDR400 EDD2516AMTA-5 (16M words × 16 bits, DDR400) Description Pin Configurations The EDD2508AMTA-5 is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8

BT122

Contextual Info: PRELIMINARY DATA SHEET 256M bits DDR SDRAM EDD2508AMTA 32M words x 8 bits EDD2516AMTA (16M words × 16 bits) Description Pin Configurations The EDD2508AM is a 256M bits Double Data Rate (DDR) SDRAM organized as 8,388,608 words × 8 bits × 4 banks. The EDD2516AM is a 256M bits DDR

uPD45D128164G5-C75-9LG

Abstract: uPD45D128442G5-C75-9LG uPD45D128442G5-C80-9LG uPD45D128842G5-C75-9LG uPD45D128842G5-C80-9LG
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD45D128442, 45D128842, 45D128164 128 M-bit Synchronous DRAM with Double Data Rate 4-bank, SSTL_2 Description The µPD45D128442, 45D128842, 45D128164 are high-speed 134,217,728 bits synchronous dynamic randomaccess memories, organized as 8,388,608x4x4, 4,194,304x8x4, 2,097,152x16x4 (word x bit x bank), respectively.

E014

Abstract: NEC 524 UPD4516161D UPD4516161DG5
Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516161D 16M-bit Synchronous DRAM 2-banks, LVTTL Description The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words x 16 bits × 2 banks respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421-PC, 4516821-PC, 4516161-PC 16M-bit Synchronous DRAM for PC SDRAM Lite Description The µPD4516421-PC, 4516821-PC, 4516161-PC are high-speed 16,777,216-bit synchronous dynamic randomaccess memories, organized as 2,097,152 x 4 × 2, 1,048,576 × 8 × 2 and 524,288 × 16 × 2 word × bit × bank ,

Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT /¿ P D 4 5 6 4 4 4 1 -A 7 5 , 4 5 6 4 8 4 1 -A 7 5 64M-bit Synchronous DRAM, 133MHz 4-bank, LVTTL Description The ^¡PD4564441-A75, 4564841-A75 are high-speed 67,108,864-bit synchronous dynamic random-access memories, organized as 4,194,304 x 4 x 4 and 2,097,152 x 8 x 4 word x bit x bank , respectively.

E014

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4516161D 16M-bit Synchronous DRAM 2-banks, LVTTL EO Description The µPD4516161D is high-speed 16,777,216-bit synchronous dynamic random-access memory, organized as 524,288 words x 16 bits × 2 banks respectively. The synchronous DRAMs achieved high-speed data transfer using the pipeline architecture.

uPD4516821AG5-A10BL-9NF

Abstract: UPD4516161AG5-A
Contextual Info: PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT µPD4516421A, 4516821A, 4516161A for Rev. B, P 16M-bit Synchronous DRAM Description The µPD4516421A, 4516821A, 4516161A are high-speed 16,777,216-bit synchronous dynamic random-access memories, organized as 2,097,152 x 4 × 2, 1,048,576 × 8 × 2 and 524,288 × 16 × 2 word × bit × bank , respectively.

Contextual Info: DATA SHEET MOS INTEGRATED CIRCUIT µPD4564441-A75, 4564841-A75, 4564163-A75 64M-bit Synchronous DRAM, 133MHz 4-bank, LVTTL Description The µPD4564441-A75, 4564841-A75, 4564163-A75 are high-speed 67,108,864-bit synchronous dynamic randomaccess memories, organized as 4,194,304x4×4, 2,097,152×8×4, 1,048,576×16×4 word × bit × bank , respectively.