B04 N06 Search Results

DH11

Abstract: DH21 DH23 b09 n03 DH19 dh17 A09 N03 Dh14 dh28 Dh29
Contextual Info: OFFICIAL - 9/17/97 CBGA Footprints Rev. F 603 Family CBGA C16 E04 D13 F02 D14 G01 D15 E02 D16 D04 E13 G02 E15 H01 E16 H02 F13 J01 F14 J02 F15 H03 F16 F04 G13 K01 G15 K02 H16 M01 J15 P01 L02 K04 C01 B04 B03 B02 A04 B07 J04 A10 L01 B06 E01 D08 A06 D07 B01 B05

b09 n03

Abstract: RTU A08 b04 n03 A09 N03 RTU A01 1553 bus controller b04 n06 a13 trans a06 n03
Contextual Info: 000 BUS-65612 ILC DATA DEVICE CORPORATION«_ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACTFACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The B U S -6561 2isa 16M H z single chip dual re dund ant M IL-S TD -1553 Bus Controller BC , Remote Terminal Unit

A09 N03

Abstract: b09 n03 b04 n03 b06 n03 65612
Contextual Info: 000 BU-65612 lue DATA DEVICE CORPORATION _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL Contact Factory For BUS-65612 AND BUS MONITOR CMOS SOS Version DESCRIPTION The BU-65612 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Con­ troller (BC), Remote Terminal Unit (RTU),

K0212

Abstract: A09 N03
Contextual Info: 000 BUS-65612 ILC DATA DEVICE CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The BUS-65612 is a 16 MHz single chip dual redund ant M IL-S TD -1553 Bus C ontroller BC , Remote Terminal Unit

b09 n03

Abstract: A09 N03 B07 P03
Contextual Info: 1.6 PowerPC 604e Microprocessor Pinout Listings Table 10 provides the pinout listing for the 604e CBGA package. Table 10. Pinout Listing for the CBGA Package Signal Name Pin Number Active I/O A[0—31 ] C16, E04, D13, F02, D14, G01, D15, E02, D16, D04, E13,

Contextual Info: D _ DC i/:'1! Z,W ; VJ«- BUS-65612 ILC DATA DEVICE CORPORATION _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION The BUS-65612 is a 16 MHz single chip dual re dund ant M IL-S TD -1553 Bus

A09 N03

Abstract: a06 n03 RTU A08 b09 n03 ddc bus-66312 BUS-66312 66312
Contextual Info: 000 BUS-66312 ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT F E A TU R E S • C O M P A T IB L E W ITH M IL-S T D -1750 C PU s • C O M P A T IB L E W ITH M O TO R O LA , INTEL, A N D Z IL O G C PU s • C O M P A T IB L E W ITH D D C

Contextual Info: BBS BU-65612 ILC DATA DEVICE CORPORATION«— MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL Contact Factory For BUS-65612 AND BUS MONITOR CM O S S O S Version FEATURES DESCRIPTIO N The BU-65612 ¡s a 16 M H z single chip dual redundant M IL-ST D -1 553 B u s C o n ­

RTU A08

Abstract: SA4M
Contextual Info: 000 BU-65612 ' ILC DATA DEVICE CORPORATION»- MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL Contact Factory For BUS-65612 AND BUS MONITOR CMOS SOS Version FEATURES DESCRIPTION The BU-65612 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Con­ troller (BC), Remote Terminal Unit (RTU),

A09 N03

Abstract: a06 n03
Contextual Info: □00 BUS-65612 ILC DATA DEVICE CORPORATION _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACTFACTORY AND BUS MONITOR FOR MORE INFORMATION FEATURES DESCRIPTION T h e B U S -6 5 6 1 2 is a 16 M H z sin g le c h ip All m e ssa g e tra n sfe r tim in g , D M A, and

Contextual Info: 000 BUS-65612 ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL CONTACT FACTORY AND BUS MONITOR FOR MORE INFORMATION FEA TU R ES DESCRIPTION T h e B U S -6 5 6 1 2 is a 16 M H z sin g le ch ip d u a l r e d u n d a n t M IL -S T D -1 5 5 3 B u s

b09 n03

Abstract: B07 P03
Contextual Info: 1. 6 Pow erPC 604e M icroprocessor Pinout Listings The following sections contain the pinout listings for the 604e C4-CQFP and BGA packages. 1.6.1 P i n o u t L i s t i n g for t h e C 4 - C Q F P P a c k a g e Table 10 provides the pinout listing for the 604e C4-CQFP package.

bck-01

Abstract: RTU A08 BCK01 ILC Data Device 65610 65611 mcl d01 BUS-65600 A09 N03 BUS-65610
Contextual Info: □01 4, > 7 BUS-65610 _ ILC DATA DEVICI CORPORATION_ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR APPROX. Vs ACTUAL SIZE FEATURES • DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit

TEA 1732

Abstract: A09 N03
Contextual Info: 1.6 PowerPC 603e Microprocessor Pinout Listings The following sections provide the pinout listings for the 603e CQFP and BGA packages. 1.6.1 Pinout Listing for the CQFP Package Table 10 provides the pinout listing for the 603e CQFP package. Table 10. Pinout Listing for the 240-pin CQFP Package

Contextual Info: ^ 001 4, x y BUS-65610 _ ILC DATA DEVICE CORPORATION_ _ _ MIL-STD-1553 BUS CONTROLLER REMOTE TERMINAL AND BUS MONITOR FEATURES DESCRIPTION The BUS-65610 is a 16 MHz single chip dual redundant MIL-STD-1553 Bus Controller BC , Remote Terminal Unit (RTU) and Bus Monitor (MT). Packaged

b09 n03

Abstract: A09 N03 YA11 D803 yb05 L0722 L0623 k0312 apl 117 YA16
Contextual Info: Am29C334 CMOS Four-Port Dual-Access Register File PRELIMINARY 64 x 18 Bit Wide Register File The Am29C334 is a 64 x 18-bit, dual-access RAM with two read ports and two write ports. Pipelined Data Path The Am29C334 can be configured to support either a non-pipelined data path similar to the Am29334 or a

dh03

Abstract: DH07 DH09 AB-04 MDATA62 dh23 AD-05 T14 N03 w04 68 mark w06
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz. • 83.33 MHz. • Synchronous DRAM interface operates at the processor bus speed with support for ECC.

DH-04

Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz IBM25CPC700BB3B66 . • 83.33 MHz (IBM25CPC700BB3B83). • Synchronous DRAM interface operates at the

RTU A08

Abstract: 308-815
Contextual Info: GE C P L E S S E Y !SEMICONDUCTORS I A DVAN CE INFORMATION 3088-1.5 December 1991 CT2566 MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT G P S C T 2 5 6 6 M IL -S T D -1 5 5 3 to M ic ro p ro c e s s o r Interface Unit sim plifies the CPU to 1553 Data Bus interface.

Contextual Info: 1. 6 Pow erPC 603e M icroprocessor Pinout Listings The following sections contain the pinout listings for the 603e CQFP and CBGA packages. 1.6.1 P i n o u t L is tin g for th e C Q F P P a c k a g e Table 10 provides the pinout listing for the 603e CQFP package.

RTU A08

Abstract: RTU A01 4k x 4 ram microprocessor types intel 8080 63d08 MARK A03 d1137 d1541 Z8000
Contextual Info: GEC P L E S S E Y A D VAN CE INFORMATION I S E M I C O N D U C T O R S ¡_ 3 088-1.5 Decem ber 1991 CT2566 MIL-STD-1553 TO MICROPROCESSOR INTERFACE UNIT G P S C T 2 5 6 6 M IL -S T D -1 5 5 3 to M ic ro p ro c e s s o r Interface Unit sim plifies the CPU to 1553 Data Bus interface.

bae rad750

Abstract: RAD750 rad750 user manual bae RAD750 processor A22 CGA board ae09 cga 624 hs01 SECDED mcc w04
Contextual Info: HS-01 12/2000 Version: 1.1 Technical Data 1 Power PCI PowerPC/PCI/Memory Controller Hardware Specifications The Power PCI chip developed by BAE SYSTEMS provides a radiation hardened PowerPC microprocessor common hardware reference platform CHRP compliant bridge between the PowerPC

b09 n03 transistor

Abstract: A09 N03 TRANSISTOR POWER BGA PACKAGE thermal resistance Zo transistor h07 K15 thermistor transistor k08 PID9t-604e powerpc 604e advanced information ibm604 thermistor m15
Contextual Info: 7/30/97 G522-0325-00 IBM Order Number Rev 1.3 Y Advance Information R PowerPC 604e TM RISC Microprocessor Family: IM IN The PID9t-604e microprocessor is an implementation of the PowerPCTM family of reduced instruction set computer (RISC) microprocessors. In this document, the term

b09 n03

Abstract: MDATA62 DH03 DH-04 aa09
Contextual Info: . CPC700 Memory Controller and PCI Bridge Features map essential to making it appear like a device but does not preclude it from being a host. • PowerPC 60x/7xx bus. • 66.66 MHz IBM25CPC700BB3B66 . • 83.33 MHz (IBM25CPC700BB3B83). • Synchronous DRAM interface operates at the