B 201 S Search Results

25275

Contextual Info: TE X A S IN S T R { L I N / I N T F O T s D Ê| 0033=127 TELECOM CIRCUITS r 3 T-75-11-37 TCM2101/2 PCM REPEATER DECEMBER 1982 Features GND M • • • • • • • PCM Signal amplification Two ALBO taps High Q or Low Q clock extraction Decision time adjustment

ttl 74100

Abstract: 74100 74100 Latch IC TTL 74100 54100
Contextual Info: TYPES SN54W0, SN74100 8-BIT BISTASIE UTCHES ttl MSI B U L L E T IN N O . D L - S 7211830, D E C E M B E R 1972 " S J 5 Ï Ï » . . . J OR W PACKAGE SNS4100 . . . i OB N PACKAGE TOP VIEW logic FUNCTION TABLE (Each Latch) INPUTS G L H H H X L •^ . .

Contextual Info: SN74ALS874B, SN74ALS876A, SN74AS874, SN74AS876 SN54ALS874B, SN54AS874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS D2661. APRIL 1982 - REVISED MAY 198$ 3-State Buffer-Type Outputs Drive Bus-Lines Directly S N 5 4A LS 8 74 B , S N 5 4 A S 8 7 4 . . . J T PACKAGE

47C400B

Abstract: 47c200b 47C101
Contextual Info: TOSHIBA TMP47C990E, TMP47C990G CMOS 4-Bit Microcontroller TMP47C990E, TMP47C990G The 47C990, which is equipped with an EPROM as program memory, is a piggyback type evaluator chip used for develop­ ment and operational confirmation of the 47C200B/400B and

Contextual Info: SN74LVC16240 16-BIT BUFFER/DRIVER WITH 3-STATE OUTPUTS SCAS312 - NOVEMBER 1993 - REVISED MARCH 1994 Member of the Texas Instruments Wldebus Family EPIC™ Enhanced-Performance Implanted CMOS Submicron Process Typical V q l p (Output Ground Bounce) < 0.8 V at VCc = 3.3 V, TA = 25°C

Q193

Abstract: lj11
Contextual Info: PRODUCT PREVIEW SN54AS29821, SN54AS29822, SN74AS29821, SN74AS29822 10-BIT BUS INTERFACE FLIP FLOPS WITH 3 STATE OUTPUTS D 2 8 2 5 , MAY 1986 Designed to be Interchangeable w ith A M D A M 2 9 8 2 1 and A M 2 9 8 2 2 SN 54A S29821 . . . JT PACKAGE SN 74A S29821 . . . DW OR NT PACKAGE

TLP508

Abstract: thyristor 072 0043 sl 1008 transistor thyristor st 103
Contextual Info: 9. Reliability 9.1 General In recent years, as the application fields for photo couplers expand, more discussions are being made on reliability. For reliability improvement, it is insufficient to perform strinct process management and to have reliability tests such as life test and environmental tests. It is necessary to

ta31087

Contextual Info: REGULATOR AND PERIPHERAL TENTATIVE DATA SYSTEM REGULATOR 1C FOR CORDLESS TELEPHONE 2 independent regulators and m icrocom puter pow er on a chip, very suitable fo r a handset o f cordless telephone. FEATURES • W atch-dog-tim er fun ction • 2 independent regulators

Contextual Info: TC74LCX16373AFT LOW-VOLTAGE 16-BIT D-TYPE LATCH WITH 5V TOLERANT INPUTS A N D OUTPUTS T h e TC74LCX16373AFT is a high p erform an ce C M O S 16bit D-TVPE LATCH. Designed fo r use in 3.3 V o lt systems, it achieves high speed o p e ra tio n w h ile m ain tain in g the

TCD1702C

Abstract: ccd linear toshiba
Contextual Info: TO SHIBA _ TCD1702C TENTATIVE TOSHIBA CCD LINEAR IMAGE SENSOR CCD Charge Coupled Device TCD1702C The TCD1702C is a high sensitive and low dark current 7500 elements CCD image sensor. The sensor is designed for facsimile, imagescanner and

TLCS-47

Contextual Info: TOSHIBA TMP47P452VN, TMP47P452W For program operation, the programming is achieved by using with EPROM programm er TMM2764AD type and adapter socket (BM1120, BM1121). CMOS 4-Bit Microcontroller TMP47P452VN, TMP47P452VF The 47P452V is the OTP microcontroller with 32kbits PROM.

74BCT29827

Abstract: LT 7242
Contextual Info: SN74BCT29827A, SN74BCT2982BA 10-BIT BUFFERS AND BUS DRIVERS WITH 3-STATE OUTPUTS D 2 9 7 7 . APRIL 1 9 8 7 -R E V IS E D M A Y 1 9 8 8 DW OR N T P A C K A G E 1 BiCMOS Design Substantially Reduces Standby Current TO P V IEW G ill 1 A id 2 A2 C 3 A3 C 4

54AC11181

Abstract: TI018
Contextual Info: 54AC11181, 74AC11181 ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS T I0184— D 3119, APRIL 1989— REVISED MARCH 1990 Flow-Through Architecture to Optimize PCB Layout 54AC11181 . . . JT PACKAGE 74AC11181 . . . DW OR NT PACKAGE TOP VIEW Minimize High-Speed Switching Noise

Contextual Info: 54ACT11874, 74ACT11874 DUAL 4-BIT D-TYPE EDGE-TRIGGERED FLIP-FLOPS WITH 3-STATE OUTPUTS D3447, MAR CH 1990-R E V IS E D O C TO BER 1990 54A C T 11 8 74 . . . J T P A C K A G E Inputs are TTL-Voltage C om patible 74A C T 11 8 74 . . . D W O R N T P A C K A G E

74AC11873

Contextual Info: 54AC11873, 74AC11873 DUAL 4-BIT D-TYPE LATCHES WITH 3-STATE OUTPUTS • 54A C 11 8 73 . . . J T P A C K A G E 3-State Buffer-Type Outputs Drive Bus 74AC 11B73 . . . D W OR N T P A C K A G E Lines Directly TOP V IE W • Bus-Structured Pinout • Flow -Through A rchitecture O ptim izes PCB

Contextual Info: TYPES SN54ALS677, SN54ALS678. SN74ALS677, SN74ALS678 ADDRESS COMPARATORS D 2 6 6 1 , J U N E 1 9 8 2 — R E V IS E D D E C E M B E R 1 9 8 3 S N 54A LS 677 . . . JT PACKAGE SN 74A LS 677 . . . .NT PACKAGE TOP VIEW • A L S 6 7 7 is a 16 -b it to 4-B it Comparator w ith Enable

SN54ALS192

Abstract: 74ALS192
Contextual Info: SN54ALS192, SN54ALS193, SN74ALS192. SN74ALS193 SYNCHRONOUS 4 BIT UP/DOWN COUNTERS DUAL CLOCK WITH CLEAR D 2 6 6 1 , D EC EM BE R 1 9 8 2 - R E V IS E O M A Y • Look-A head C irc u itry Enhances Cascaded C ounters • Fully S ynchronou s in C o u n t M odes

S1818

Abstract: 74AS181B
Contextual Info: PRODUCT PREVIEW SN54AS181B, SN74AS181B ARITHMETIC LOGIC UNITS/FUNCTION GENERATORS D 2661, DECEM BER 1 9 8 5 - REVISED M AY 1986 S N 5 4 A S 1 8 1 B . . . J T OR J W P A C K A G E S N 7 4 A S 1 8 1 B . . . N OR NT P A C K A G E P a c k a g e O p tio n s In clu d e C o m p a c t 3 0 0 -m il

A1051

Contextual Info: TMS27C291, TMS27C292 16.384-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORIES TMS27PC291 16,384-BIT PROGRAMMABLE READ-ONLY MEMORY SEPTEM BER 1986 —REVISED APRIL 1988 Organization . . . 2K x 8 J AND N PA C KA G E Pin Compatible with Existing 2K x 8 Bipolar/High-Speed CM OS EPROMs

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

TC8600F

Abstract: 1126to PHOTO INTERRUPT ROTATING SPEED SENSOR 360rpm magnetic head FDD
Contextual Info: TOSHIBA INTEGRATED CIRCUIT TC8600F TECHNICAL DATA TC8600F Fl o pp y Disk Mechanism Controller INTRODUCTION The FDMC-II TC8600F is a one chip C-MOS LSI in which the control logic of FLOPPY DISK DRIVE (FDD), together with the 4-bit CPU and required random logic.