ATM RECOMMENDATION AVAILABILITY Search Results

Contextual Info: ATM Cell-Based UTOPIA Level 1 Interface Megafunction Solution Brief 35 Target Applications: Networking Data Communications Multiplexers Cross-Connects Family: FLEX 10K Vendor: PLD Applications 14 Rue Soleillet 75971 Paris Cedex 20 France Tel. 33 01-40-33-79-98

AF-VTOA-0113

Abstract: BTS G29 TAAD08JU2 transistor w2d AG10 AH11 AJ11 TAAD08JU21BCLS2-DB 31N40
Contextual Info: Preliminary Data Sheet July 2002 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM adaptation process for next-generation wireless base transmission station BTS , base station controller (BSC), node B, radio network

Contextual Info: Preliminary Data Sheet April 2002 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine 1 Features • System-on-a-chip integrated circuit supports ATM adaptation process for next-generation wireless base transmission station BTS , node B, base station controller (BSC), radio network controller

lcd 5421

Abstract: A15351 TAAD08JU2 ntt japan cid 1616f
Contextual Info: Preliminary Data Sheet August 18, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

Contextual Info: Data Sheet, Rev. 1 November 25, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

SA513

Contextual Info: Preliminary Data Sheet November 27, 2002 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • ■ ■ ■ System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

Contextual Info: Preliminary Data Sheet July 2, 2002 TAAD08JU2 T1/E1/J1 ATM Processor 1 Features • ■ ■ ■ System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

operation39

Contextual Info: Preliminary Data Sheet August 23, 2002 TAAD08JU2 T1/E1/J1 ATM Processor 1 Features • ■ ■ ■ System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

MC92053

Abstract: ONU block diagram Reed Solomon decoder IC MC68360 MC92052 MC92052CG MCM6206 MCM6306 convolutional interleaver
Contextual Info: MOTOROLA Order this Data Sheet by MC92052/D SEMICONDUCTOR TECHNICAL DATA MC92052 Product Brief MC92052 FTTC User Framer The MC92052 is a peripheral device for the user side of an FTTC drop. It is composed of downstream and upstream TC-sublayer functionality with UTOPIA compliant ATM-layer ports.

AF-TM-0121

Abstract: ATML CATM 180 nm CMOS standard cell library AMI
Contextual Info: Preliminary Data Sheet May 8, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

Contextual Info: Data Sheet August 11, 2003 TAAD08JU2 T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

Contextual Info: Data Sheet, Rev. 1 November 25, 2003 TAAD08JU21BCLUL3A T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

ATML

Abstract: agere apc CDM TYPE 271 180 nm CMOS standard cell library AMI
Contextual Info: Data Sheet, Rev. 1 November 25, 2003 TAAD08JU21BCL-L3A T1/E1/J1 ATM Processor, Versions 2.1 and 3.1 1 Features • System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller (BSC), node-B, radio network controller

Contextual Info: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLSU3A-DB AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 1 Features 3 Description • System-on-a-chip integrated circuit supports lowspeed ATM adaptation process for next-generation wireless base transmission station BTS , base station controller (BSC), node B, radio network controller (RCN), and voice gateway applications.

Contextual Info: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLS2-DB SAR-2K AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 1 Features 3 Description • System-on-a-chip integrated circuit supports lowspeed ATM adaptation process for next-generation wireless base transmission station BTS , base station controller (BSC), node B, radio network controller (RCN), and voice gateway applications.

A9KX

Abstract: TAAD08JU21BCLSL3A-DB
Contextual Info: Preliminary Data Sheet May 9, 2003 TAAD08JU21BCLSL3A-DB AAL2/AAL5 SAR Engine, Versions 2.1 and 3.1 1 Features 3 Description • System-on-a-chip integrated circuit supports lowspeed ATM adaptation process for next-generation wireless base transmission station BTS , base station controller (BSC), node B, radio network controller (RCN), and voice gateway applications.

MOTOROLA SCR

Abstract: atm recommendation availability
Contextual Info: P R O D U C T B R I E F ATM Buffer Manager V2.1 The ABM PXB 4330 Traffic Management Device is well accepted in a variety of applications where extensive ATM Traffic Management capabilities are required in either distributed or centralized system architectures of Enterprise and CO

Ericsson Marconi

Abstract: Ericsson battery backup system SMA1CP MSP SNCP Line Interfaces packets EN61000-4-3 SE-126 2048KHZ STM-1 and STM-4
Contextual Info: SMA Series 4: SMA1CP, SMA4CP, STM-1 and STM-4 Customer premises add/drop multiplexers ● ● Space-saving and easy deployment with an ultra-compact footprint Versatile delivery platforms: ● ● – Full range of conventional traffic interfaces from 2Mbit/s to STM-1

Contextual Info: ICs for Communications Synchronous Digital Hierarchy Transceiver SDHT PXB 4240 Version 1.2 Preliminary Data Sheet 10.96 T4240-X V 12- • fiEBSbDS 0Cnfl737 343 ■ -7600 \ Edition 10.96 This edition was realized using the software system FrameMaker . Published by Siemens AG,

NDS TANDBERG E5610 MPEG-2 encoder

Abstract: e5610 nds tandberg data sheet e5610 ATECOM tandberg e5610 mpeg-2 manual tandberg e5610 ASX-1000 tandberg MPEG-2 TS to DS3 alcatel fan tray
Contextual Info: ATM VISION -3 Date: July 2000 ATM VISION 3 ATecoM GmbH This page is intentionally left blank Page 2 of 36 09/05/00 ATM VISION 3 ATecoM GmbH Contents 1 2 3 3.1 3.2 4 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 5 5.1 5.2 6 6.1 6.2 6.3 7 8 Summary .5

TE19M

Abstract: i80C186 T4240 PXB43202
Contextual Info: ICs for Communications Synchronous Digital Hierarchy Transceiver SDHT PXB 4240 Version 1.2 Preliminary Data Sheet 10.96 T4240-XV12-P1-7600 Edition 10.96 This edition was realized using the software system FrameMaker. Published by Siemens AG, Bereich Halbleiter, MarketingKommunikation, Balanstraße 73,

b.a private admission form

Abstract: ST ARM CORE 1825 0255 indala lcd 5421 1673 lucent newport 215-3 1647 lucent FIC PMX CTC ASSOCIATES scr ctc 313
Contextual Info: Preliminary Data Sheet August 2001 TAAD08JU2 Newport T1/E1/J1/J2 ATM Processor 1 Features 2 Physical System-on-a-chip integrated circuit supports lowspeed ATM access for next-generation wireless base transmission station BTS , base station controller BSC), and remote access concentrator

PCM30 PDH system

Abstract: echo cancellation motorola EASY954 PCM30 Digital Echo delay by cmos logic
Contextual Info: P R O D U C T B R I E F The Smart Integrated Digital Echo Canceller SIDEC PEB 20954 is a highly sophisticated single chip solution for T1/E1 echo cancellation. It incorporates leading edge CMOS technology as well as Infineon’s many years experience with Telecommunication ICs.

TCA 321

Abstract: TCA 345 CRC-32 G781 GR-253-CORE PM5352 30f-310 TETRA terminal
Contextual Info: PM5352 S/UNI STAR DATA SHEET PMC-1990421 ISSUE 2 SATURN USER NETWORK INTERFACE 155 STAR PM5352 S/UNI-STAR SATURN USER NETWORK INTERFACE (STAR) DATA SHEET ISSUE 2: FEBRUARY 2000 PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE