ASYNCHRONOUS Search Results

toshiba p300

Abstract: kd qa
Contextual Info: INTEGRATED T O SH IB A 8 -B IT CIRCUIT TECHNICAL TOSHIBA CMOS DIGITAL INTEGRATED CIRCUIT TC74ACT299P/F/FW DATA SILICON MONOLITHIC PIPO SHIFT REGISTER WITH ASYNCHRONOUS CLEAR The TC74ACT299 is an advanced high speed CMOS 8-BIT PIPO SHIFT REGISTER fabricated with silicon gate and

IR 30 D1

Contextual Info: SN74ALS236 64 x 4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107A-OCTOBER 1986 - REVISED SEPTEMBER 1993 Asynchronous Operation Organized as 64 Words by 4 Bits DW OR N PACKAGE TOP VIEW r NC [ 1 Data Rates From 0 to 30 MHz 3-State Outputs 16 J VCC 15 ] S O

Contextual Info: TL16C550C ASYNCHRONOUS COMMUNICATIONS ELEMENT WITH AUTOFLOW CONTROL SLLS177B- MARCH 1994 - REVISED MARCH 1996 • Programmable Auto-RTS and Auto-CTS • In Auto-CTS Mode, CTS Controls Transmitter • In Auto-RTS Mode, RCV FIFO Contents and Threshold Control RTS

Contextual Info: SN74ALS233B 16x5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SCAS253 - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs DW OR N PACKAGE TOP VIEW • 16 Words by 5 Bits OE [ 1 FULL-1 [ 2 • Data Rates From 0 to 40 MHz • Fall-Through Ti me. . . 14 ns Typ

74ALS234

Contextual Info: SN54ALS234, SN74ALS234 64 x 4 ASYNCHRONOUS FIRST-IN FIRST OUT MEMORY 0 2 9 5 8 , OCTOBER 1 9 8 6 Asynchronous Operation S N 54A LS 234 . . . J PACKAGE S N 74A LS 234 . . . 0 OR N PACKAGE Organized as 6 4 Words of 4 Bits Management Products TOP VIEW! Data Rates from 0 to 30 MHz

Contextual Info: S N 5 4 A LS 2 2 9 A , S N 7 4 A LS 2 2 9 A 1 6 x 5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES D 2 8 7 6 . M A R C H 1 9 8 6 -R E V IS E D M A Y 1 9 8 6 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits Each • Data Rates from 0 to 30 MHz

Contextual Info: SN74ALS232B 1 6 x 4 ASYNCHRONOUS FIRST IN, FIRST OUT MEMORY D3247 • Independent Asynchronous Inputs and Outputs DW OR N PACKAGE Package Options Include Plastic "Sm all O utline" Packages, Plastic Chip Carriers, and Standard Plastic 300-m il DIPs OE C TOP VIEW

Q7910

Abstract: SN74ALS2232A
Contextual Info: SN74ALS2232A 64 x 8 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORY D3091, F E B R U A R Y 1988 - R E V IS E D M A R C H 1990 Independent Asynchronous Inputs and Outputs NT PA C K A G E ITO P VIEW [ DOC D1 C D2C D3C 64 Words by 8 Bits rst Data Rates from 0 to 40 MHz

821A4

Contextual Info: SN54HCT242, SN54HCT243 SN74HCT242, SN74HCT243 QUADRUPLE BUS TRANSCEIVERS WITH 3 STATE OUTPUTS D 2 8 0 4 . M AR C H 1 9 8 4 - Inputs are TTL-Voltage Compatible • 2-W ay Asynchronous Communication Between Data Buses TO P V IE W ] G1 C 1 L J l4 H V CC 13 2 G2

CT 2048

Abstract: D8228
Contextual Info: SN74ACT7203L, SN74ACT7204L, SN74ACT7205L, SN74ACT7206L 2048 x 9,4096 x 9,8192 x 9,16384 x9 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORIES SCAS226A - FEBRUARY 1993 - REVISED SEPTEMBER 1995 Reads and Writes Can Be Asynchronous or Coincident Organization: - SN74ACT7203L - 2048 x 9

74ALS233

Contextual Info: S N 5 4 A LS 2 3 3 A , S N 7 4 A LS 2 3 3 A 1 6 x 5 ASYNCHRONOUS FIRST-IN FIRST-OUT MEMORIES D 2 8 7 6 . JA N U A R Y 1 9 8 6 - Package Options Include Plastic "Small Outline" Packages. Ceramic Chip Carriers, and Standard Plastic and Ceramic 300-mil DIPs S N 54A LS 233A . . . J PACKAGE

um611864

Contextual Info: a S amar a a P R E L IM IN A R Y - UM611864 64K X 18 Bit Synchronous High Speed CMOS SRAM Features Single +5V power supply Fast access times: 9/11 ns Current: Operating: 275mA Standby: 95mA Synchronous self-timed write Individual byte write control Asynchronous output enable

Contextual Info: SN74ACT7881 1024 x 18 CLOCKED FIRST-IN, FIRST-OUT MEMORY SCAS227C - FEBRUARY 1993 - REVISED FEBRUARY 1996 • Member of the Texas Instruments Wldebus Family • Independent Asynchronous Inputs and Outputs • Input-Ready, Output-Ready, and Half-Full Flags

741t

Abstract: L076
Contextual Info: TYPES SNS4LS242, SN54LS243, SN74LS242. SN74LS243 QUADRUPLE BUS TRANSCEIVERS • Two-Way Asynchronous Communication Between Data Bums • P-N-P Inputs Reduce D-C Loading • Hysteresis Typically 400 mV at Inputs Improves Noise Margin 8N64LS242 . . . J O R W

Contextual Info: TL16C550A ASYNCHRONOUS COMMUNICATIONS ELEMENT D3128.AUG UST1989- HEVISEDFEBRUARY 1990 • Capable o f Running w ith A ll Existing TL16C450 Software N PACKAGE TOP VIEW • A fte r Reset, A ll R egisters Are Identical to the TL16C450 Register Set DOC l U D1C

Contextual Info: SN74ALS229B 16 x 5 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SPAS09Q - MARCH 1990 - REVISED JUNE 1992 • Independent Asychronous Inputs and Outputs • 16 Words by 5 Bits • Data Rates From 0 to 40 MHz • Fall-Through Time. . . 14 ns "typ • 3-State Outputs

NS16C450N

Contextual Info: TL16C450 ASYNCHRONOUS COMMUNICATIONS ELEM ENT 0 3 0 9 6 , M A R C H 1 9 8 8 - R E V IS E O A P R IL 1 9 8 9 N DUAL-IN-LINE PACKAGE • Programmable Baud Rate Generator Allows Division of Any Input Reference Clock by 1 to 216 - 1 and Generates an Internal 16 X

Contextual Info: UT54ACS193/UT54ACTS193 Radiation-Hardened Synchronous 4-Bit Up-Down Dual Clock Counters FEATURES • • • • • • • • • • PIN OUTS 16-Pin D IP Top View Look-ahead circuitry enhances cascaded counters Fully synchronous in count modes Parallel asynchronous load for modulo-N count lengths

54ACS

Abstract: LT26
Contextual Info: a d v a n c e in fo r m a t i o n \ J T 54ACS 193/UT54ACTS 193 Radiation-Hardened Synchronous 4-Bit Up-Down Counters FEATURES • • • • • • • • • • Look-ahead circuitry enhances cascaded counters Fully synchomous in count modes Parallel asynchronous load for modulo-N count lengths

Video RAM

Abstract: TMS55165
Contextual Info: TMS55165 262144 BY 16-BIT MULTIPORT VIDEO RAM SMVS165B-AUGUST1992-flEVISED JANUARY 1993 DGH PACKAGEt TOP VIEW DRAM : 262 144 Words x 16 Bits SAM: 256 Words x 16 Bits Dual Port Accessibility - Simultaneous and Asynchronous Access From the DRAM and SAM Ports

Contextual Info: SN74ACT2235 1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148E - DECEMBER 1990 - REVISED APRIL 1998 • Independent Asynchronous Inputs and Outputs • Access Times of 25 ns With a 50-pF Load • Data Rates up to 50 MHz • Low-Power Advanced CMOS Technology

Contextual Info: SN74ALS236 64x4 ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY SDAS107C - OCTOBER 1986 - REVISED APRIL 1998 DW OR N PACKAGE TOP VIEW • Asynchronous Operation • Organized as 64 Words by 4 Bits • Data Rates up to 30 MHz • 3-State Outputs • Package Options Include Plastic

TMP68661

Contextual Info: TOSHIBA UC/UP S4E D • c]0,ì 7 2 4 Iì G 0 5 4 G 7 5 TO SHIBA Ö24 * T 0 S 3 TM P68661 1. INTRODUCTION - r - is - 3 1 - a n The TMP68661 enhanced program m able communications interface (EPCI) is a universal synchoronous/asynchronous data communications controller chip th at is an

74als2238

Contextual Info: SN74ALS2238 32 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN FIRST-OUT MEMORY D3501, A P R IL 1990 N PACKAQE TOP VIEW Independent Asychronous Input« and Outputs Bidirectional RSTK 32 Word« by 9 BK. Each * Data Rate« from 0 to 40 MHz * F a ll-T h ro u g h T im e . . . 2 2 n « iy p