APPLICATION OF PROGRAMMABLE ARRAY LOGIC Search Results

APPLICATION OF PROGRAMMABLE ARRAY LOGIC Result Highlights (5)

Part	Manufacturer	Description	Download
LQW18CN4N9D0HD	Murata Manufacturing Co Ltd	Fixed IND 4.9nH 2600mA POWRTRN	PDF
LQW18CNR33J0HD	Murata Manufacturing Co Ltd	Fixed IND 330nH 630mA POWRTRN	PDF
DFE322520F-R47M=P2	Murata Manufacturing Co Ltd	Fixed IND 0.47uH 8500mA NONAUTO	PDF
DFE32CAH4R7MR0L	Murata Manufacturing Co Ltd	Fixed IND 4.7uH 2800mA POWRTRN	PDF
LQW18CNR27J0HD	Murata Manufacturing Co Ltd	Fixed IND 270nH 750mA POWRTRN	PDF

APPLICATION OF PROGRAMMABLE ARRAY LOGIC Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
palce 16v8z amd Abstract: 16v8 programming Guide mach 1 family amd palce16v8 programming guide 22v10z 16V8 16V8Z 20RA10 20V8 26V12 Contextual Info: Selecting the Correct CMOS PLD—An Overview of Advanced Micro Devices’ CMOS PLDs Application Note INTRODUCTION The purpose of this application note is to provide a survey of AMD’s CMOS PLDs Programmable Logic Devices . This includes both PAL (Programmable Array	Original		PDF
vhdl code for multiplexer 256 to 1 using 8 to 1 Abstract: vhdl code for asynchronous fifo vhdl code for multiplexer 4 to 1 using 2 to 1 vhdl code for multiplexer 8 to 1 using 4 to 1 by vhdl code for multiplexer 256 to 1 Contextual Info: Implementing RAM Functions in FLEX 10K Devices November 1995, ver. 1 Introduction Application Note 52 The Altera FLEX 10K family provides the first programmable logic devices PLDs that contain an embedded array. The embedded array is composed of a series of embedded array blocks (EABs) that can efficiently	Original		PDF
multiplier 4 x 4 Contextual Info: Implementing Multipliers in FLEX 10K Devices March 1996, ver. 1 Introduction Application Note 53 The Altera FLEX 10K embedded programmable logic device PLD family provides the first PLDs in the industry with an embedded array. The embedded array consists of a series of embedded array blocks (EABs) that	Original		PDF
PLS151N Abstract: PLS151 PLS151A Contextual Info: PLS'151 Signetics Field-Programmable Gate Array 18 X 15 X 12 Signetics Programmable Logic Product Specification Application Specific Products • Series 20 DESCRIPTION FEATURES The PLS151 is a single level logic ele ment, consisting of 15 AND gates with	OCR Scan	PLS151 PLS151N PLS151A	PDF
pin configuration of logic gates Abstract: logic gates pin configuration "OR Gates" application of programmable array logic and gates or gates PLS173 24 SIGNETICS signetics PLHS173 Contextual Info: Signetics PLHS173 Field Programmable Logic Array 2 2 x 4 2 x 10 Signetics Programmable Logic Application Specific Products • Series 24 DESCRIPTION The PLHS173 is a high-speed version of the PLS173 FPLA. The Signetics stateof-the-art Oxide Isolated Bipolar fabrica	OCR Scan	PLHS173 PLHS173 PLS173 22x42x10) pin configuration of logic gates logic gates pin configuration "OR Gates" application of programmable array logic and gates or gates 24 SIGNETICS signetics	PDF
CHIPX Abstract: CX5000 CX50041 CX50101 CX50211 CX50331 CX50561 CX50841 CX51191 CX51761 Contextual Info: DATASHEET CX5000 0.18um Structured ASIC Product Description The 0.18um CX5000 is an ASIC that utilizes the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs while reducing application	Original	CX5000 CX5000 CEC034 CHIPX CX50041 CX50101 CX50211 CX50331 CX50561 CX50841 CX51191 CX51761	PDF
CX5000 Abstract: CHIPX cmos ic and gates datasheet sram 200mhz 8k CX50041 CX50101 CX50211 CX50331 CX50561 CX50841 Contextual Info: DATASHEET CX5000 0.18um Structured ASIC Product Description The 0.18um CX5000 is an ASIC that utilizes the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs while reducing application	Original	CX5000 CX5000 CEC034 CHIPX cmos ic and gates datasheet sram 200mhz 8k CX50041 CX50101 CX50211 CX50331 CX50561 CX50841	PDF
format .rbf Abstract: Quartus format .rbf format .pof AM29DL32XD EP20K1000E EPXA10 excalibur Board Contextual Info: System Development Tools for Excalibur Devices January 2003, ver. 1.0 Introduction Application Note 299 The Excalibur embedded processor devices achieve a new level of system integration from the inclusion of an embedded processor system within a field programmable gate array FPGA . Such an integration	Original		PDF
CHIPX Abstract: CX5000 CX50101 CX50211 CX50331 CX50561 CX50841 CX502 Contextual Info: Data Sheet CX5000 0.18-µm Structured ASIC Product Description The 0.18-µm CX5000 is an ASIC that uses the combination of an advanced metal programmable gate array and optimized EDA system to implement high performance ASIC designs, while reducing application	Original	CX5000 CX5000 1-800-95-CHIPX 0247-5k-080-C CHIPX CX50101 CX50211 CX50331 CX50561 CX50841 CX502	PDF
spansion altera Abstract: S25FLxxx EP3SE50 EP2C35-6 Contextual Info: Connecting Spansion SPI Serial Flash to Configure Altera FPGAs Application Note By Frank Cirimele 1. Introduction Altera FPGAs are programmable logic devices used for basic logic functions, chip-to-chip connectivity, signal processing, and embedded processing. These devices are programmed and configured using an array of	Original		PDF
DS012 Abstract: MC15 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL Contextual Info: APPLICATION NOTE  DS012 v1.0 January 20, 2000 CoolRunner XPLA3 CPLD 14* Advance Product Specification Features Family Overview • The CoolRunner XPLA3 (eXtended Programmable Logic Array) family of CPLDs is targeted for low power systems that include portable, handheld, and power sensitive applications. Each member of the XPLA3 family includes Fast	Original	DS012 CS280 PQ208 TQ144 CS144 VQ100 XCR3032XL XCR3064XL XCR3128XL XCR3256XL DS012 MC15 PT16 XCR3032XL XCR3064XL XCR3128XL XCR3256XL XCR3384XL	PDF
format .pof Abstract: format .rbf Eprom, altera MasterBlaster Quartus format .rbf AM29DL32XD EP20K1000E EPXA10 vhdl sdram excalibur Board Contextual Info: System Development Tools for Excalibur Devices June 2003, ver. 1.1 Introduction Application Note 299 The Excalibur devices achieve a new level of system integration from the inclusion of an embedded processor system within a field programmable gate array FPGA . Such an integration increases the demands placed on	Original		PDF
S25FL128* spansion Abstract: simple spi flash spi flash what the difference between the spartan and virtex ADM6384x27D2 virtex5 Xilinx spartan xc3s400a FPGA 456 interfacing adsp with spartan-3 fpga XAPP951 Contextual Info: Connecting Spansion SPI Serial Flash to Configure Xilinx® FPGAs Application Note by Frank Cirimele and Jocelyn Carroue 1. Introduction Xilinx FPGAs are programmable logic devices used for basic logic functions, chip-to-chip connectivity, signal processing, and embedded processing. These devices are programmed and configured using an array of	Original		PDF
CNT4A Abstract: TA139 Contextual Info: f ACT 1 Field Programmable Gate Arrays I Features Description • U p to 2000 G ate Array Gates 6000 PLD /LCA ™ equivalent gates T he A C T ™ 1 family of field program mable gate arrays (FPGAs) offers a variety of package, speed, and application combinations.	OCR Scan	20-Pin CNT4A TA139	PDF

application of programmable array logic Abstract: verilog code for implementation of eeprom altera application note Contextual Info: January 1996, ver. 1 Introduction Application Note 51 Gate arrays have historically been used for high-volume designs. However, Altera’s programmable logic devices PLDs are an ideal alternative for prototyping gate array designs and for high-volume	Original	-AN-051-01 application of programmable array logic verilog code for implementation of eeprom altera application note	PDF
PLS159 Abstract: AN15 PLS159A Contextual Info: Philips Semiconductors Programmable Logic Devices Application Note PLS159A primer AN15 Issued June 1988; Revised October 1990 INTRODUCTION The PLS159A is a programmable logic sequencer which consists of four dedicated inputs, four bidirectional I/O’s, eight flip-flops,	Original	PLS159A 16-input 32-input PLS159A PLS159 AN15	PDF
PLUS405-55 Abstract: AN034 digital clock using logic gates AN-034 single one jk flipflop Maximum Megahertz Project PLUS405 LEAST16 Contextual Info: Philips Semiconductors Programmable Logic Devices Application Note PLUS405-55 – the ideal high speed interface INTRODUCTION Philips Semiconductors PLUS405–55 is ideal for high performance microprocessor interfacing applications. Being a programmable integrated circuit, it adapts to	Original	PLUS405-55 PLUS405 AN034 Brv818 PLUS405-55 AN034 digital clock using logic gates AN-034 single one jk flipflop Maximum Megahertz Project LEAST16	PDF
application of programmable array logic Contextual Info: Basic Design with PLDs Advanced Micro Devices INTRODUCTION The Programmable Array Logic device, commonly known as the PAL device, was invented at Monolithic Memories in 1978. The concept for this revolutionary type of device sprang forth as a simple solution to the	Original		PDF
EPM9320 Abstract: EPM9560 Contextual Info: MAX 9000 Programmable Logic Device Family June 1996, ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX	Original	12-ns EPM9320 EPM9560	PDF
EPX880-10 Abstract: EPX8160-10 EPX8160-12 EPX880-12 Contextual Info: FLASHlogic Programmable Logic Device Family June 1996, ver. 2 Features. Data Sheet • ■ ■ ■ High-performance programmable logic device PLD family – SRAM-based logic with shadow FLASH memory elements fabricated on advanced CMOS technology – Logic densities from 1,600 to 3,200 usable gates (see Table 1)	Original	24V10 84-Pin 132-Pin EPX8160 EPX8160 208-Pin EPX880-10 EPX8160-10 EPX8160-12 EPX880-12	PDF
EPM9560 pinout Contextual Info: MAX 9000 Programmable Logic Device Family June 1996, ver. 4 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX	Original	12-ns EPM9560 pinout	PDF
EPM3032A Abstract: EPM3064A EPM3128A EPM3256A Contextual Info: MAX 3000A Programmable Logic Device Family October 2001, ver. 2.1 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices PLDs built on a MAX® architecture (see Table 1)	Original		PDF
fan speed control 8051 Abstract: EPM3256A 144-Pin PLCC/TQFP Package Pin-Out Diagram compared CMOS TTL Logic Family Specifications data sheet for 3 input xor gate epm3064 epm3064A TTL LOGIC DATA BOOK EPM3032A EPM3128A Contextual Info: MAX 3000A Programmable Logic Device Family March 2001, ver. 2.0 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High–performance, low–cost CMOS EEPROM–based programmable logic devices PLDs built on a MAX® architecture (see Table 1)	Original		PDF
AF14 Abstract: EPM9320 EPM9560 280-Pin Contextual Info: Includes MAX 9000A MAX 9000 Programmable Logic Device Family February 1998, ver. 5.01 Features. Data Sheet • ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices PLDs built on third-generation Multiple Array MatriX	Original		PDF

APPLICATION OF PROGRAMMABLE ARRAY LOGIC Search Results

APPLICATION OF PROGRAMMABLE ARRAY LOGIC Result Highlights (5)

APPLICATION OF PROGRAMMABLE ARRAY LOGIC Datasheets Context Search

palce 16v8z amd

vhdl code for multiplexer 256 to 1 using 8 to 1

multiplier 4 x 4

PLS151N

pin configuration of logic gates

CHIPX

CX5000

format .rbf

CHIPX

spansion altera

DS012

format .pof

S25FL128* spansion

CNT4A

application of programmable array logic

PLS159

PLUS405-55

application of programmable array logic

EPM9320

EPX880-10

EPM9560 pinout

EPM3032A

fan speed control 8051

AF14