ALVCH16601 Search Results

IDT74ALVCH162601

Abstract: IDT74ALVCH16601 SO56-2
Contextual Info: ALVCH16601 3.3V CMOS IDT74ALVCH162601 18-BIT UNIVERSAL BUS ADVANCE INFORMATION TRANSCEIVER WITH 3-STATE OUTPUTS Integrated Device Technology, Inc. FEATURES: data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable

Contextual Info: 3.3V CMOS 18-BIT UNIVERSAL BUSTRANSCEIVER WITH 3-STATE OUTPUTS AND BUS HOLD FEATURES: - combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable

Contextual Info: ALVCH16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: ALVCH16601 DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK o (Output Skew) < 250ps

74LVC05

Abstract: 7400 datasheet 2-input nand gate 74LVC05A LVC1G04 transistor x1 pv 25 inverter board design pv 74ALVC1G04 74ALVCH244 7400 nand gate series 74ALVC1G14
Contextual Info: Selector Guide for ALVC/LVC Products the leading provider of high-performance logic. From single-gate to 32-bit, IDT is your source for ALVC/LVC logic. Today’s designers are developing the most challenging telecommunications, networking and PC products ever designed

IDT74ALVCH16601

Abstract: SO56-2
Contextual Info: ALVCH16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER EXTENDED COMMERCIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD ALVCH16601 FEATURES: 0.5 MICRON CMOS Technology Typical tSK 0 (Output Skew) < 250ps

62601

Contextual Info: 3.3V C M O S 18-B IT U N IV E R S A L BUS T R A N S C E I V E R WITH 3-STATE OUTPUTS data flow in transparent, latched and clocked modes. Data flow in each direction is controlled by output-enable OEAB and OEBA , latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. The clock can be controlled by

Contextual Info: FEATURES: - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0) 0.635mm pitch SSOP, 0.50mm pitch TSSOP, and 0.40mm pitch TVSOP packages Extended commercial range of - 40°C to + 85°C

Contextual Info: 3.3V CMOS 18-BIT UNIVER­ SAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD IDT74A L VCH16601 FE A T U R E S : - - 0.5 MICRON CMOS Technology Typical tsK o (Output Skew) < 250ps ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model (C = 200pF, R = 0)

IDT74ALVCH16601

Contextual Info: ALVCH16601 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS 18-BIT UNIVERSAL BUS TRANSCEIVER WITH 3-STATE OUTPUTS AND BUS-HOLD FEATURES: ALVCH16601 DESCRIPTION: • 0.5 MICRON CMOS Technology • Typical tSK o (Output Skew) < 250ps

Contextual Info: fü P E R IC O ALVCH16601 M .

Contextual Info: 3.3V CMOS 18-BIT UNIVERSAL BUSTRANSCEIVER WITH 3-STATE OUTPUTS AND BUS HOLD FEATURES: - ALVCH16601 combines D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable

Contextual Info: f ü PERICOM ALVCH16601 18-Bit Universal Bus Transceiver With 3-State Outputs Product Features: Product Description: