ADC 12 ALUMINIUM Search Results

ADC 12 aluminium

Abstract: ABS0949 ABD0031 ABD0031 issue F draka fileca adb 541 XADC12-001 ARC 231 ABS0958 abs1354
Contextual Info: F PV28T Aluminium Cables ABS 1354 ADB/ADC/ADD data sheet Very Light weight, Wires 180°C Arc Tracking resistant CONSTRUCTION : CHARACTERISTICS : Environmental : Operating temperature : - 55°C to + 180°C ambient temperature + current heating Resistant to :

D 92 M - 02 DIODE

Abstract: atmel 702
Contextual Info: Features • • • • • • • • • • • • • • • • • • Up to 2 Gsps Sampling Rate Power Consumption: 4.6 W 500 mVpp Differential 100 Ω or Single-ended 50 Ω ±2 % Analog Inputs Differential 100 Ω or Single-ended 50 Ω Clock Inputs

686C CAPACITOR

Abstract: AI203
Contextual Info: EV10AS008B 10-bit 2.2 Gsps ADC Datasheet - Preliminary Specification Features • • • • • • • • • • • • • 10-bit Resolution ADC 2.2 Gsps Sampling Rate Ascending Compatibility with e2v AT84AS008 10-bit 2.2 Gsps ADC 500 mVpp Full-scale Analog Input Range

AT84AD001C

Contextual Info: AT84AD001C Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD004BVTD

Abstract: AT84AD004B Digital Oscilloscope Preamplifier 144L AT84AD004 LQFP144 AT84AD004BVT
Contextual Info: AT84AD004B Dual 8-bit 500 Msps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

radar 77 ghz

Contextual Info: AT84AD004B Dual 8-bit 500 Msps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD001B

Abstract: AT84AD001BVEPW AT84AD001BITD AT84AD001BV
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

LQFP-144 footprint

Abstract: Digital Oscilloscope Preamplifier AT84AD001B AT84AD001TD-EB LQFP144 schematics c band satellite receiver
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

Digital Oscilloscope Preamplifier

Abstract: LQFP-144 footprint AT84AD001B AT84AD001TD-EB LQFP144 schematics c band satellite receiver
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

satellite tuner sharp

Abstract: AT84AD001B
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD001BVEPW

Abstract: AT84AD001B AT84AD001BV
Contextual Info: AT84AD001B Dual 8-bit 1 Gsps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

AT84AD004BVTD

Abstract: Digital Oscilloscope Preamplifier AT84XAD004TD LQFP144 AT84AD004 AT84AD004B ADC digital calibration time interleaved
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

LQFP-144 footprint

Abstract: Digital Oscilloscope Preamplifier LQFP-144 144L AT84AD004 AT84AD004CTD AT84AD004TD-EB AT84AD004VTD AT84XAD004TD LQFP144
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

Digital Oscilloscope Preamplifier

Abstract: NEC 2561 nec 2561 block diagram AT84AD001B AT84AD001TD-EB LQFP144 schematics ps satellite receiver
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

Digital Oscilloscope Preamplifier

Abstract: LQFP-144 LQFP-144 footprint AT84AD001B AT84AD001TD-EB LQFP144 3968 diode surface AT84AD001 618FS schematics c band satellite receiver
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

Contextual Info: AT84AD004B Dual 8-bit 500 Msps ADC Datasheet 1. Features • • • • • • • • • Dual ADC with 8-bit Resolution 500 Msps Sampling Rate per Channel, 1 Gsps in interleaved Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only)

2153D

Abstract: AT84AD001B AT84AD001TD-EB LQFP144 FISO
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

2153d

Abstract: LDN DIODE Digital Oscilloscope Preamplifier LQFP-144 footprint AT84AD001B AT84AD001TD-EB LQFP144
Contextual Info: Features • • • • • • • • • Dual ADC with 8-bit Resolution 1 Gsps Sampling Rate per Channel, 2 Gsps in Interlaced Mode Single or 1:2 Demultiplexed Output LVDS Output Format 100Ω 500 mVpp Analog Input (Differential Only) Differential or Single-ended 50Ω PECL/LVDS Compatible Clock Inputs

MC9S08AW60

Abstract: microswitch pushbutton 74HC08 SMD dcbv R46 ARCO 74HC86 74HC04D generator dynamo MC9S08AW48 MC9S08AW32
Contextual Info: MC9S08AW60 Controller Board User Manual HCS08 Microcontrollers DRM090 Rev.0 10/2007 freescale.com Preface 0.1 0.2 0.3 0.4 0.5 Audience . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .

ETX-7111

Abstract: CXA3003BR-T6 TCX04 cell phone jammer cell phone jammer circuit Sony Semiconductor t6 C0806 CXA3003BR RC-1009B direct digital synthesizer for phone Jammer
Contextual Info: Messrs. M l Date of Issue 1998. 1.21 Issued No. 9801007 SHIPMENT SPECIFICATION Product Name CXA3003BR-T6 [Function] Baseband analog processing IC for dual-mode _ CDMA-FM cellular phone_ Receipt Stamp SONY CORPORATION Semiconductor Company

gps tod format

Abstract: marking codes transistors 2F2 TRANSISTOR J 6815 EQUIVALENT TS83102 5404A j 6815 transistor at84as008cgl
Contextual Info: Features • • • • • • • • • • • • • • 10-bit Resolution ADC 2.2 Gsps Sampling Rate Seamless Ascending Compatibility with Atmel TS83102G0B 10-bit 2 Gsps ADC 500 mVpp Full-scale Analog Input Range 100Ω Differential or 50Ω Single-ended Analog input and Clock Input

gps tod format

Abstract: atmel 948
Contextual Info: Features • • • • • • • • • • • • • • 10-bit Resolution ADC 2.2 Gsps Sampling Rate Seamless Ascending Compatibility with Atmel TS83102G0B 10-bit 2 Gsps ADC 500 mVpp Full-scale Analog Input Range 100Ω Differential or 50Ω Single-ended Analog input and Clock Input

marking codes transistors 2F2

Abstract: BDC Marking gps tod format AT84AS008 AI203 AT84AS008CGL AT84CS001 RO4003 TS83102G0B
Contextual Info: Features • • • • • • • • • • • • • • 10-bit Resolution ADC 2.2 Gsps Sampling Rate Seamless Ascending Compatibility with TS83102G0B 10-bit 2 Gsps ADC 500 mVpp Full-scale Analog Input Range 100Ω Differential or 50Ω Single-ended Analog input and Clock Input

Diode smd f6

Abstract: control 220V using Parallel port J1 HE10 microcontroller ST7 datasheet windows epromer 3 phase motor soft starter circuit diagram AC 220v Motor Speed Controller AC 240V Motor Speed Controller he10 connector he10 SOCKET
Contextual Info: ST7 FAMILY DEVELOPMENT KIT MDT2 VERSION GETTING STARTED Release 1.0 NOVEMBER 1998 DOC- ST7MDT2-DVP 11 USE IN LIFE SUPPORT DEVICES OR SYSTEMS MUST BE EXPRESSLY AUTHORIZED. STMicroelectronics PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF