ACTEL A1280A UNUSED PIN Search Results

Contextual Info: Æ ic te ! RadTolerant Field Programmable Gate Arrays - m Features • Programming Technology Prevents Reverse Engineering and Design Theft General Characteristics • • TestedTotal Ionizing Dose TID Survivability Level • Packages: 132-Pin, 172-Pin, 196-Pin, and 256-Pin Ceramic

Contextual Info: RadTolerant Field Programmable Gate Arrays Features • Programming Technology Prevents Reverse Engineering and Design Theft General Characteristics • • TestedTotal Ionizing Dose TID Survivability Level • Packages: 132-Pin, 172-Pin, 196-Pin, and 256-Pin Ceramic

Contextual Info: Æ ic t e ! v 3 .0 - m RadTolerant Field Programmable Gate Arrays Features • 100%Resource Utilization with 100%Pin-Locking General Characteristics • Secure Programming Technology Pre\ents Reverse Engineering and Design Theft

CQFP 256 PIN actel

Abstract: RT1280A A1280A VKS rt1280 A1020B ACTEL A1280A A1020 transistor A1280A-CQ172C RT1460 actel 172 cqfp
Contextual Info: v3.1 RadTolerant FPGAs Features General Characteristics • • • • • • Tested Total Ionizing Dose TID Survivability Level No Single Event Latch-Up Below a Minimum LET (Linear Energy Transfer) Threshold of 80 MeV-cm2/mg for All RT (RadTolerant) Devices

RT14100A

Abstract: rt1280 VKS FPGA CQFP 172 RT1280A CQFP 172 PIN 172-PIN A1280A VKS RT1460 VKS FPGA CQFP 106 A1020B
Contextual Info: v3.1 RadTolerant FPGAs Features General Characteristics • • • • • • Tested Total Ionizing Dose TID Survivability Level No Single Event Latch-Up Below a Minimum LET (Linear Energy Transfer) Threshold of 80 MeV-cm2/mg for All RT (RadTolerant) Devices

RT1280A-CQ172E

Abstract: RT1280A-CQ172 RT1280A
Contextual Info: RadTolerant Field Programmable Gate Arrays F e a tu re s • Secure Programming Technology Engineering and Design Theft G e n e r a l C h a r a c te r is t ic s Prevents Reverse • Permanently Programmed for Instantaneous Operation on Power-Up • Tested Total Ionizing Dose TID Survivability Level

A1225

Abstract: A1225A A1240 A1240A A1240A-2 A1280 A1280A actel a1240 Actel A1225A
Contextual Info: ACT 2 Family FPGAs Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • Datapath Performance at 105 MHz 1 • 16-Bit Accumulator Performance to 39 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages

HCL ME 1014

Contextual Info: Æ 9c t e ! P re lim in a ry RadTolerant RAD-PAK Field Programmable Gate Arrays F e a tu re s R a d ia tio n C h a r a c te r is t ic s • RAD-PAK® Package Technology from Space Electronics, Inc. • Improved Total Ionizing Dose TID Survivability - Can Improve TID 2-10x Over Standard Package

Actel a1280

Abstract: A1225 A1225A A1240 A1240A A1240A-2 A1280 A1280A actel a1280a unused pin actel a1240
Contextual Info: v4.0.1 ACT 2 Family FPGAs Fe a t ur es • Datapath Performance at 105 MHz • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • 16-Bit Accumulator Performance to 39 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL

TA138

Abstract: TA280 3SB24 TA1225A 176-CPGA dece2x4
Contextual Info: ACTEL CORP Æ Ic M b?E » I • 01^24^ DDDGÔ33 TS1 ■ ACT ACT 2 Field Programmable Gate Arrays Features Description • The ACT™ 2 family represents Actel’s second generation of field programmable gate arrays FPGAs . The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules.

Contextual Info: Æ ic te ! RadTolerant RAD-PAK Field Programmable Gate Arrays - m Features Radiation • • Characteristics RAD-PAK® Package Technology from Space Electronics, Inc. Improved Total Ionizing Dose TID Survivability - Can Im prove TI D 2-10x Over Standard Package

Actel a1280

Abstract: VKS FPGA CQFP 172 actel 1020 A1020 smd TRANSISTOR 5962-9215601MXA 5962-9096503MTC equivalent transistor A1020 y 7 b Actel A1020 ACTEL A1010 actel 1020 datasheet
Contextual Info: Military Field Programmable Gate Arrays Features ACT 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Device Sizes from 1200 to 10,000 gates up to 25,000 PLD equivalent gates • Up to 4, Fast, Low-Skew Clock Networks

A3200DX

Abstract: DIODE 044 1334 smd 5962-9215602MXA 5962-9552001MYC A1280XL A32100DX A32140DX 5962-9215602MYA A32300DX Resistor SMD 310
Contextual Info: HiRel Field Programmable Gate Arrays Features 3200DX • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • 100 MHz System Logic Integration • Device Sizes from 1200 to 30,000 gates • Highest Speed FPGA SRAM, up to 4 Kbits Configurable

A1020 Y

Abstract: smd transistor E5 GHL 88
Contextual Info: Military Field Programmable Gate Arrays Features A C T 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family • System Performance to i( MHz over Military Temperature

DA1225A

Abstract: diode SD1 03c
Contextual Info: Ic M ACTM2 Field Programmable Gate Arrays Features • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages 16-Bit Accumulator Performance to 39 MHz • Replaces up to eighty 20-Pin PAL Packages

5962-9096504MTA

Contextual Info: Military Field Programmable Gate Arrays Features A C T 3 Features Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family Device Sizes from 1200 to 10,000 gates up to 25,000 PLD

Contextual Info: MAY 1 g «93 Æ lc lm ll ACT 2 Field Programmable Gate Arrays Features Description • H ie ACT™ 2 family represents Actel’s second generation of field programmable gate arrays FPGAs . The ACT 2 family presents a two-module architecture, consisting of C-modules and S-modules.

Contextual Info: ACT 2 Family FPGAs F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages Two In-Circuit Diagnostic Probe Pins Support Speed

132-PIN CERAMIC PIN GRID ARRAY CPGA

Abstract: A1280A-PG176B 32200D smd transistor JJ
Contextual Info: = * 4 c t e ml HiRel FPGAs Features 3200DX • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • 100 MHz System Logic Integration • Device Sizes from 1200 to 20,000 gates • Highest Speed FPGA SRAM, up to 2.5 Kbits Configurable

transistor D883

Abstract: CQFP 172 PIN vr 201 act 1014 5962-9550801MYA A1020BL mya 111
Contextual Info: HiRel FPG A s Features 3 2 0 0 DX • Highly Predictable Performance with 100 Percent • 100 MHz System Logic Integration Automatic Placement and Routing • Highest Speed FPGA SFIAM, up to 2.5 Kbits Configurable Dual-Port SFIAM • Device Sizes from 1200 to 20,000 gates

100CPGA

Contextual Info: ACT 2 Field Programmable Gate Arrays F e a tu re s • Up to 8000 Gate Array Gates 20,000 PLD equivalent gates • Datapath Performance at 105 MHz • Replaces up to 200 TTL Packages • Replaces up to eighty 20-Pin PAL Packages • Two In-Circuit Diagnostic Probe Pins Support Speed

cpga dimensions

Abstract: 132-PIN CERAMIC PIN GRID ARRAY CPGA actel a1240 5962-9322101MXC 10KRESISTOR NET IC LM 384 gn
Contextual Info: HiRel Field Programmable Gate Arrays F ea t u re s 3200DX * Highly Predictable Performance with 100 Percent Autom atic Placement and Routing * 100 MHz System Logic Integration * Device Sizes from 1200 to 30,000 gates * Highest Speed FPGA SRAM, up to 4 Kbits Configurable

5962-9552102MYA

Abstract: 5962-9215601MYA 5962-9322101M 5962-9215602mxa A1020B-PG84B 5962-9552102mxa 152 LSK
Contextual Info: Military Field Programmable Gate Arrays Features ACT 3 Features • Highly Predictable Performance with 100 Percent Automatic Placement and Routing • Highest-Performance, Highest-Capacity FPGA Family • Device Sizes from 1200 to 10,000 gates up to 25,000 PLD

transistor A1010

Abstract: A1020 transistor ACTEL A1010 32140DX A1010 A1020 A1225A A1225XL A1240A A1240XL
Contextual Info: Testing and Programming Actel Field Programmable Gate Arrays FPGAs Testing has long been a struggle for users of masked gate arrays. To avoid board-level, system-level, or even possible field failures, the system designer must expend great effort in developing test vectors for gate array designs. Even after the