A101 TRANSISTOR Search Results
A101 TRANSISTOR Result Highlights (5)
| Part | ECAD Model | Manufacturer | Description | Download | Buy |
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| BLA1011-300 |
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BLA1011-300 - 300W LDMOS Avionics Power Transistor |
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| 54F151LM/B |
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54F151 - Multiplexer, 1-Func, 8 Line Input, TTL |
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| ICL7667MJA |
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ICL7667 - Buffer/Inverter Based MOSFET Driver, CMOS, CDIP8 |
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| 93L422ADM/B |
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93L422A - 256 x 4 TTL SRAM |
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| 93425ADM/B |
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93425 - 1K X 1 TTL SRAM |
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A101 TRANSISTOR Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
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siemens s7-300 battery replacement
Abstract: siemens 300 Modular PLC features service manual SITOP siemens sitop power 20 electrical diagram siemens sitop power 40 siemens sitop power 10 6EP1931-2FC01 Maintenance Manual siemens sitop 6EP1437-3BA00 circuit diagram
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E86060-K1010-A101-A2-7600 E86060-K4921-A101-A3-7600 E86060-K4678-A111-B8-7600 E86060-D4001-A510-D2-7600 80/ST E86060-K4680-A101-C1-7600 SINA9-7600 siemens s7-300 battery replacement siemens 300 Modular PLC features service manual SITOP siemens sitop power 20 electrical diagram siemens sitop power 40 siemens sitop power 10 6EP1931-2FC01 Maintenance Manual siemens sitop 6EP1437-3BA00 circuit diagram | |
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Contextual Info: Cascadable Amplifier 5 to 100 MHz A101 / SMA101 V2 Features • • • • Product Image HIGH OUTPUT POWER: +23 dBm TYP. HIGH THIRD ORDER IP: +36 dBm (TYP.) HIGH SECOND ORDER IP: +64 dBm (TYP.) LOW NOISE FIGURE: 3 dB (TYP.) Description The A101 RF amplifier is a discrete hybrid design, which uses |
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SMA101 MIL-STD-883 SMA101 CA101 | |
siemens simatic op17 manual
Abstract: SIMATIC Field PG IPC547D Siemens s7 1200 manual IPC427C SIWATOOL RS232 Cable IPC677C siemens a5e00 MTBF SIEMENS electric motor S7-200 cpu 215
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E86060-K6710-A101-B7-7600 80/ST E86060-K4680-A101-B9-7600 E86060-K4678-A111-B8-7600 E86060-K2410-A111-A8-7600 E86060-K8310-A101-A8-7600 E86060-K6850-A101-C3 P4-7600 siemens simatic op17 manual SIMATIC Field PG IPC547D Siemens s7 1200 manual IPC427C SIWATOOL RS232 Cable IPC677C siemens a5e00 MTBF SIEMENS electric motor S7-200 cpu 215 | |
a101 transistor
Abstract: A101 CA101 SMA101
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A101/SMA101 SMA101 CA101 a101 transistor A101 CA101 SMA101 | |
a101 transistorContextual Info: A101/SMA101 5 TO 100 MHZ TO-8 CASCADABLE AMPLIFIER • HIGH OUTPUT POWER: +23 dBm TYP. · HIGH THIRD ORDER IP: +36 dBm (TYP.) · HIGH SECOND ORDER IP: +64 dBm (TYP.) · LOW NOISE FIGURE: 3 dB (TYP.) Typical Performance @ 25°C Specifications (Rev. Date: 3/02)* |
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A101/SMA101 SMA101 CA101 a101 transistor | |
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Contextual Info: CY7C1361A CY7C1363A 256K x 36/512K x 18 Synchronous Flow-Thru Burst SRAM Features • • • • • • • • • • • • • • • • • • Fast access times: 6.0, 6.5, 7.0, and 8.0ns Fast clock speed: 150, 133, 117, and 100MHz Fast OE access times: 3.5 ns and 4.0 ns |
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CY7C1361A CY7C1363A 36/512K 100MHz CY7C1361A/CY7C1363A | |
CY7C1362A
Abstract: GVT71512B18
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CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 36/512K CY7C1361A/GVT71256B36 CY7C1363A/GVT71512B18 CY7C1362A GVT71512B18 | |
CY7C1362A
Abstract: GVT71512D18
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CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 36/512K CY7C1360A/GVT71256D36 CY7C1362A GVT71512D18 | |
CY7C1367A
Abstract: GVT71512C18 4947a
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CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 36/512K 100-Pin 1-85050-A 119-Lead CY7C1367A GVT71512C18 4947a | |
CY7C1360A
Abstract: CY7C1362A
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CY7C1360A CY7C1362A 36/512K CY7C1360A CY7C1362A | |
CY7C1328A
Abstract: GVT71256F18
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CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 36/256K CY7C1328A/GVT71256F18, CY7C1348A/GVT71128F36 CY7C1328A GVT71256F18 | |
CY7C1328A
Abstract: GVT71256F18
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CY7C1328A/GVT71256F18 CY7C1348A/GVT71128F36 36/256K CY7C1328A GVT71256F18 | |
CY7C1367A
Abstract: GVT71512C18
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CY7C1366A/GVT71256C36 CY7C1367A/GVT71512C18 36/512K CY7C1367A GVT71512C18 | |
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Contextual Info: 1CY7C1329 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 PRELIMINARY 256K x 36/512K x 18 Pipelined SRAM Features • • • • • • • • • • • • • • • • • • and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positive-edge-triggered Clock Input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining |
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1CY7C1329 CY7C1360A/GVT71256D36 CY7C1362A/GVT71512D18 36/512K | |
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CY7C1357A
Abstract: GVT71512ZB18
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1CY7C1357A CY7C1355A/GVT71256ZB36 CY7C1357A/GVT71512ZB18 256Kx36/512Kx18 CY7C1357A GVT71512ZB18 | |
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Contextual Info: CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 256K x 36/512K x 18 Pipelined SRAM with NoBL Architecture Features • Zero Bus Latency, no dead cycles between Write and Read cycles • Fast clock speed: 200, 166, 133, 100 MHz • Fast access time: 3.2, 3.6, 4.2, 5.0 ns |
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CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 36/512K operation1354A/GVT71256ZC36 CY7C1354A/GVT71256ZC36 CY7C1356A/GVT71512ZC18 | |
CY7C1355A
Abstract: CY7C1357A GVT71512ZB18
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CY7C1357A CY7C1355A 36/512K CY7C1355A/GVT71256ZB36 CY7C1355A/CY7C1357A CY7C1355A CY7C1357A GVT71512ZB18 | |
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Contextual Info: PRELIMINARY CY7C1344A/GVT7164B36 64K x 36 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • The CY7C1344A/GVT7164B36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip |
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CY7C1344A/GVT7164B36 CY7C1344A/GVT7164B36 536x36 | |
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Contextual Info: 346A PRELIMINARY CY7C1346A/GVT7164D36 64K x 36 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • The CY7C1346A/GVT7164D36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry |
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CY7C1346A/GVT7164D36 CY7C1346A/GVT7164D36 536x36 | |
r3381
Abstract: R3498 buv49 MP150s tipl763 TIC263M transistor BD245 BDW85-S buv48s BD250C-S
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OT-93 BLBF40 MP150SG, MG15G-1040R, cusV47-S BUV48 BUV48A BUV48A-S r3381 R3498 buv49 MP150s tipl763 TIC263M transistor BD245 BDW85-S buv48s BD250C-S | |
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Contextual Info: 344A PRELIMINARY CY7C1344A/GVT7164B36 64K x 36 Synchronous Burst SRAM Features • • • • • • • • • • • • • • • • The CY7C1344A/GVT7164B36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry and a 2-bit counter for internal burst operation. All synchronous inputs are gated by registers controlled by a positiveedge-triggered Clock input CLK . The synchronous inputs include all addresses, all data inputs, address-pipelining Chip |
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CY7C1344A/GVT7164B36 CY7C1344A/GVT7164B36 536x36 | |
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Contextual Info: PRELIMINARY CY7C1346A/GVT7164D36 64K x 36 Synchronous Pipelined Burst SRAM Features • • • • • • • • • • • • • • • • • The CY7C1346A/GVT7164D36 SRAM integrates 65,536x36 SRAM cells with advanced synchronous peripheral circuitry |
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CY7C1346A/GVT7164D36 CY7C1346A/GVT7164D36 536x36 | |
R3381
Abstract: R3498 R3381-S a101 transistor BDW85-S buv49 transistor 1015 TIPL763 TIC263D 883 transistor
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OT-93 BLBF40 MP150SG, MG15G-1040R, cusV47-S BUV48 BUV48A BUV48A-S R3381 R3498 R3381-S a101 transistor BDW85-S buv49 transistor 1015 TIPL763 TIC263D 883 transistor | |
4918A
Abstract: CY7C1327C GVT71256DA18
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CY7C1347C/GVT71128DA36 CY7C1327C/GVT71256DA18 18/128K 4918A CY7C1327C GVT71256DA18 | |