TXC06125ACPL Search Results
TXC06125ACPL Datasheets (2)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
---|---|---|---|---|---|---|---|
TXC-06125ACPL |
![]() |
Receiver, XBERT Device Bit Error Rate Generator Receiver | Original | 184.91KB | 34 | ||
TXC-06125-ACPL |
![]() |
Bit Error Rate Generator Receiver | Original | 184.91KB | 34 |
TXC06125ACPL Price and Stock
Transwitch Corporation TXC-06125ACPL |
|||||||||||
Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
![]() |
TXC-06125ACPL | 200 |
|
Get Quote | |||||||
Transwitch Corporation TXC-06125-ACPL |
|||||||||||
Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
![]() |
TXC-06125-ACPL | 100 |
|
Get Quote | |||||||
![]() |
TXC-06125-ACPL | 28 |
|
Buy Now | |||||||
TRANS TXC-06125-ACPLIC,ERROR CORRECTION FOR TELECOM,LDCC,44PIN,PLASTIC |
|||||||||||
Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
![]() |
TXC-06125-ACPL | 6 |
|
Buy Now |
TXC06125ACPL Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
---|---|---|---|
Contextual Info: TXC06125ACPL/B Linear ICs Dedicated/Special Application Linear Circuit statusû Military/High-RelY P D Max. (W)800m Nom. Supp (V)5.0 Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)70 Package StyleQCC-J Mounting StyleS Pinout Equivalence Code44-185 |
Original |
TXC06125ACPL/B Code44-185 Pins44 NumberLN04400185 25ACPL/B | |
Contextual Info: TXC06125ACPL Linear ICs Dedicated/Special Application Linear Circuit statusû Military/High-RelN P D Max. (W)800m Nom. Supp (V)5.0 Minimum Operating Temp (øC)0 Maximum Operating Temp (øC)70 Package StyleQCC-J Mounting StyleS Pinout Equivalence Code44-185 |
Original |
TXC06125ACPL Code44-185 Pins44 NumberLN04400185 C06125ACPL | |
Contextual Info: BACK XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET FEATURES DESCRIPTION • Bit-serial, nibble-parallel, and byte-parallel interface capability, selectable via control bits The Bit Error Rate Generator/Receiver XBERT VLSI device is a microprocessor-programmable multi-rate |
Original |
TXC-06125 OC-12/STM-4) TXC-06125-MB | |
RD4AContextual Info: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET Preliminary FEATURES = — — — - = • Serial, nibble, or byte wide interface capability • Transmit and receive clock rate: 100 Hz to 52.00 MHz serial, byte, nibble I/O (All telecom rates |
OCR Scan |
TXC-06125 T0041S2 RD4A | |
Contextual Info: XBERT Device Bit Error Rate Generator Receiver TXC-06125 DATA SHEET FEATURES DESCRIPTION - = The Bit Error Rate Generator/Receiver XBERT VLSI device is a microprocessor-programmable multi-rate test pattern generator and receiver on a single chip. It is used for testing the performance of digital communica |
OCR Scan |
TXC-06125 TXC-06125-M | |
Contextual Info: X B E R T Devi ce Bit Error Rate Generator Receiver TXC-061 25 DATA SH EET FEATURES ^ DESCRIPTION • Bit-serial, nibble-parallel, and byte-parallel interface capability, selectable via control bits The Bit Error Rate Generator/Receiver XBERT VLSI device is a microprocessor-programmable multi-rate |
OCR Scan |
TXC-061 TXC-06125-M | |
G753
Abstract: 74F32 TXC-02021 TXC-06125 TXC-06125-ACPL TXC06125
|
Original |
TXC-06125 TXC-06125-MB G753 74F32 TXC-02021 TXC-06125 TXC-06125-ACPL TXC06125 |