T49FC Search Results

1117z

Abstract: IDT49FCT805A idt49fct8058 T49FC
Contextual Info: I D T 4 9 F C T 8 G 5 80 6 A Dat a B o o k A, S e c t i o n 6. 30, Pag e 1 FAST CMOS BUFFER/CLOCK DRIVER T49FCT805/A T49FCT806/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • The T49FC T805/A and ID T49FC T806/A are clock drivers built using advanced CEMOS , a dual metal CMOS

Contextual Info: T49FCT805/A T49FCT806/A FAST CMOS BUFFER/CLOCK DRIVER Integrated D evice Technology, Inc. DESCRIPTION: FEATURES: ‘H eartb eat’ monitor output T h e ID T 4 9 F C T 8 0 5 /A an d ID T 4 9 F C T 8 0 6 /A are clock drivers built using advanced dual m etal C M O S technology.

L39c

Abstract: IDT49C403 signal path designer
Contextual Info: HIGH SPEED 16-BIT REGISTER WITH SPC ^T49FCT618 ?49FC T618A id FEATURES: DESCRIPTION: • High-speed non-inverting 16-bit parallel data register for any data path, control path or pipelining application • Read back path from the data output back to the data input

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER T49FCT3805/A FEATURES: DESCRIPTION: • • • • • • • • • • • The FCT3805/A is a 3.3 volt, non-inverting clock driver built using advanced dual metal CMOS technology. The device consists of two banks of drivers, each with a 1:5 fanout and its

Contextual Info: T49FCT805/A FAST CMOS BUFFER/CLOCK DRIVER COMMERCIAL TEMPERATURE RANGE FAST CMOS BUFFER CLOCK/DRIVER DESCRIPTION: FEATURES: − − − − − − − − − − − T49FCT805/A 0.5 MICRON CMOS Technology Guaranteed low skew < 700ps max. Low duty cycle distortion < 1ns (max.)

S1054

Abstract: 49FCT804 1d481 S1055
Contextual Info: HIG H-SPEED TRI-PORT BUS MULTIPLEXER jÿdt Integrated Device Technology, Inc PRELIMINARY IDT 49FCT804/A FEATURES: DESCRIPTION: • H igh-speed, 10 b it x 3 p o rl Bus M ultiplexer • A llo w s b id ire ctio n a l co m m u n ica tio n betw een a ny 2 ports

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER T49FCT805/A T49FCT806/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: 0.5 MICRON CMOS Technology Guaranteed low skew < 700ps max. Low duty cycle distortion < 1ns (max.) Low CMOS power levels TTL compatible inputs and outputs

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER T49FCT805/A T49FCT806/A FEATURES: DESCRIPTION: • 0.5 M ICRO N CM O S Technology • Guaranteed low skew < 700ps max. • • Low duty cycle distortion < 1 ns (max.) Low CM O S power levels • • • TTL compatible inputs and outputs

T805C

Abstract: ic t805
Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER T49FCT805/A T49FCT806/A In te g r a t e d D e v ic e T e c h n o lo g y , In c . FEATURES: DESCRIPTION: • 0.5 M IC R O N C M O S Technology • Guaranteed low skew < 700ps m ax. • Low duty cycle distortion < 1ns (m ax.)

IDT49FCT818

Contextual Info: HIGH-SPEED OCTAL REGISTER WITH SPC PRELIMINARY T49FCT818 T49FCT818A Integrated Device Technology, Inc. FEATURES: • • • • • • • • • High-speed, non-inverting 8 bit parallel register fo r any data path, control path or pipelining application

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER T49FCT805BT/CT T49FCT806BT/CT Integrated Device Technology, Inc. FEATURES: Military product compliant to M IL-STD-883, Class B 0.5 M ICRO N C M O S Technology Guaranteed low skew < 500ps max. DESCRIPTION: Very low duty cycle distortion < 600ps (max.)

Contextual Info: FAST CMOS BUFFER/CLOCK DRIVER T49FCT805/A T49FCT806/A Integrated Device Technology, Inc. FEATURES: DESCRIPTION: • • • 0.5 M ICRO N CM O S Technology Guaranteed low skew < 700ps max. Low duty cycle distortion < 1 ns (max.) • Low CM O S power levels

S1354

Contextual Info: 16K x 32 WRITABLE CO NTRO L STORE STATIC RAM M ODULE are c o n n e c te d to th e D inp u ts o f a n T49FC T818. The device has the serial data -in and serial d a ta -o u tp u t b its c o n n e c te d to fo rm a 32-bit Serial P rotocol C hannel register. T h e m o d u le features four

49FCT818

Abstract: IDT49C403 S106-4
Contextual Info: HIGH-SPEED OCTAL REGISTER WITH SPC FEATURES: • H igh-speed, n o n -in vertin g 8 -b it p arallel register fo r a n y d ata path, c o n tro l path o r p ip e lin in g a p p lica tio n • New, uniq u e c o m m a n d ca p a b ility w h ich a llo w s fo r m u ltip lic ity

ADSP-21160

Abstract: ADSP 21 XXX Sharc processor
Contextual Info: 11 SYSTEM DESIGN Figure 11-0. Table 11-0. Listing 11-0. Overview The DSP supports many system design options. The options implemented in a system are influenced by cost, performance, and system requirements. This chapter provides the following system design information: