The Datasheet Archive

SQT402-1 Datasheets Context Search

Catalog Datasheet MFG & Type PDF Document Tags
74LVT74

Abstract: 74LVT 74LVT74PW
Text: SOT108- 1 14-Pin Plastic SSOP -40°C to +85°C 74LVT74 DB 74LVT74 DB SOT337- 1 14-Pin Plastic TSSOP -40°C to +85°C 74LVT74 PW 74LVT74PW DH SQT402-1 1996 Aug 28 2 853-1872 17244 Philips Semiconductors , ISSUE DATE I EC JEDEC EIAJ SQT402-1 MO-153 94-07-12 95-04-04 1996 Aug 28 4 , inputs (active rising edge) 4, 10 SDO, SD1 Set inputs (active LOW) 1 , 13 RDO, RD1 Reset inputs (active LOW) 5, 6, 8, 9 Qn, Qn Data outputs LOGIC SYMBOL (IEEE/IEC) 4 & S > C1 1D R 5 3 6 2 1 ^ 9 10


OCR Scan
PDF 74LVT74 TSSOP14: SQT402-1 MO-153 74LVT 74LVT74PW
Not Available

Abstract: No abstract text available
Text: : plastic thin shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 , side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 EIAJ , to V CC1 CONDITIONS C L = 15 pF; V CC = 3.3 V TYPICAL 6 3.5 16 UNIT ns PF PF NOTES: 1 . Cpo is used , . DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 4, 9, 12 2, 5, 10, 13 3, 6, 8, 11 7 14 SYM BOL 1 A -4 A 1 B -4 B 1 Y -4 Y GND V CC NAM E AND FUNCTION Data inputs Data inputs


OCR Scan
PDF 74LV32 74LV32
inverter lg philips

Abstract: No abstract text available
Text: PACKAGE MATERIAL 14 14 14 14 DIL SO SSOP TSSOP plastic plastic plastic plastic CODE SOT27- 1 SOT108- 1 SOT337- 1 SQT402-1 1996 Feb 3-11 Philips Semiconductors Product Specification Hex inverter , input capacitance power dissipation capacitance per gate CONDITIONS CL = 50 pF Vcc = 3.3 V notes 1 , quick reference data 1 . CP D is used to determine the dynamic power dissipation (PD in (iW) PD = CP D x , 74LVCU04DB 74LVCU04PW PINNING PIN NO. 1 , 3, 5, 9, 11, 13 2, 4, 6, 8, 10, 12 7 14 SYMBOL 1A to 6A 1Y to 6Y GND


OCR Scan
PDF 74LVCU04 74LVCU04 LVCU04 inverter lg philips
Not Available

Abstract: No abstract text available
Text: -40°C to +85°C 74ABT08 PW 74ABT08PW DH SQT402-1 1995 Sep 18 _ ■711002b D01 , maximum per side are not included. OUTLINE VERSION SQT402-1 1995 Sep 18 ■REFERENCES IEC , 3, 6, 8, 11 Vcc BO [ T SYMBOL 1 ,2, 4, 5, 9, 10,12,13 E o PIN DESCRIPTION PIN , SA00342 LOGIC SYMBOL 1 2 4 5 9 10 12 13 AO 60 A1 B1 A2 B2 A3 B3 Y0 Y1 Vcc = , NORTH AMERICA 14-Pin Plastic DIP PACKAGES -40°C to +85°C 74ABT08 N 74ABT08N SOT27- 1


OCR Scan
PDF 74ABT08 SQT402-1 MO-153 711005b 00Tbfl7b
Not Available

Abstract: No abstract text available
Text: . DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SQT402-1 PIN CONFIGURATION u [T 1Q [2 1Q [3 1K [T 2Q [5 2Q [6 GND [T 13 VCC 13] 1R 12] 1CP TT] 2K TÔ ] 2R T ] 2CP T ] 2J SV00497 PIN DESCRIPTION PIN NUMBER 1 , 8, 4 , 4.4 mm SQT402-1 0 1 I I I I 2.5 I I I I I 5 mm I scale DIMENSIONS (mm are the , protrusio n s of 0.25 mm m axim um per side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES , UNIT tpHL/tpLH CL = 15 pF; VCC = 3.3 V ns fmax MHz PF PF C| C PD NOTE: 1 . Cpo is


OCR Scan
PDF 74LV107 74LV107
74LV74

Abstract: 74LV74PW
Text: SOT27- 1 14-Pin Plastic SO -40°C to +125°C 74LV74 D 74LV74 D SOT108- 1 14-Pin Plastic SSOP Type II -40°C to +125°C 74LV74 DB 74LV74 DB SOT337- 1 14-Pin Plastic TSSOP Type I -40°C to +125°C 74LV74 PW 74LV74PW DH SQT402-1 1996 Nov 20 2 This Material Copyrighted By Its Respective Manufacturer 853-1 888 , included. OUTLINE VERSION REFERENCES EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SQT402-1 MO , per flip-flop Notes 1 and 2 24 PF NOTES: 1 . Cpo is used to determine the dynamic power dissipation


OCR Scan
PDF 74LV74 74LV74 74HC/HCT74. SQT402-1 MO-153 74LV74PW
Not Available

Abstract: No abstract text available
Text: SQT402-1 1995 Sep 18 853-1809 15755 711Dfl2b GDTbflSb 7bfl Philips Semiconductors Product , interlead protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SQT402-1 1995 Sep , 71 o 72 pF Icc - 1 .Q- 70 0.4 ns Vçc ~ P 1 *n 4 12 A3 B3 GND ■Pin 7 n SYMBOL 1 ,2, 4, 5, 9, 10, 12,13 — SA00360 PIN DESCRIPTION PIN NUMBER , Vcc Positive supply voltage E Vcc A1 [7 TT) B1 (T ]Ö| B2 A2 72 & 1


OCR Scan
PDF 74ABT00 SA00360 SQT402-1 MO-153
Not Available

Abstract: No abstract text available
Text: package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 I I scale I I , . OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 EIAJ EUROPEAN PROJECTION ISSUE DATE , ; V| = GND to V CC1 CONDITIONS C L = 15 pF; V CC = 3.3 V TYPICAL 9 3.5 22 UNIT ns PF PF NOTE: 1 , 74LV125 DB 74LV125PW DH PKG. DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYM BO L 1 Ö E -4 Ö E 1A-4A 1Y-4Y GND V CC NAM E AND FUNCTION


OCR Scan
PDF 74LV125 74LV125
74LVC08

Abstract: 74LVC08PW MS-012AB SSOP14
Text: DATE I EC JEDEC EIAJ SQT402-1 MO-153 94-07-12 95-04-04 1997 Feb 03 , C| Input capacitance 5.0 PF CPD Power dissipation capacitance per gate Notes 1 and 2 50 PF NOTES: 1 . Cpo is used to determine the dynamic power dissipation (PD in nW) PD = CPD x VCC2 x fi + x (CL x , DWG NUMBER 14-Pin Plastic SO -40°C to +85°C 74LVC08 D 74LVC08 D SOT108- 1 14-Pin Plastic SSOP Type II -40°C to +85°C 74LVC08 DB 74LVC08 DB SOT337- 1 14-Pin Plastic TSSOP Type I -40°C to +85°C


OCR Scan
PDF 74LVC08 74LVC08 TSSOP14: SQT402-1 MO-153 74LVC08PW MS-012AB SSOP14
74LVC02A

Abstract: 74LVC02APW MS-012AB SSOP14 TSSOP14
Text: ISSUE DATE IEC JEDEC EIAJ SQT402-1 MO-153 94-07-12 95-04-04 1997 Aug 11 7 This Material , Power dissipation capacitance per gate Notes 1 and 2 28 PF NOTES: 1 . Cpo is used to determine the , +85°C 74LVC02A D 74LVC02A D SOT108- 1 14-Pin Plastic SSOP Type II -40°C to +85°C 74LVC02A DB 74LVC02A DB SOT337- 1 14-Pin Plastic TSSOP Type I -40°C to +85°C 74LVC02A PW 74LVC02APW DH SOT402- 1 PIN , 3B GND 8 3A SV00389 PIN DESCRIPTION PIN NUMBER SYMBOL NAME AND FUNCTION 1 ,4, 10, 13 1Y-4Y


OCR Scan
PDF 74LVC02A 74LVC02A SQT402-1 MO-153 74LVC02APW MS-012AB SSOP14 TSSOP14
74LVT20

Abstract: 74LVT20D 74LVT20PW
Text: EIAJ SQT402-1 MO-153 04 07 12 95-04-04 1996 Aug 28 7110fl2b D1D7L.D5 0fi7 , PIN NUMBER SYMBOL NAME AND FUNCTION 1 ,2,4, 5, 9, 10, 12,13 An, Bn, Cn, Dn Data inputs 6,8 Yn Data outputs 7 GND Ground (OV) 14 Vcc Positive supply voltage LOGIC SYMBOL 1 2 4 5 9 10 12 13 AO BO CO , CO DO A1 B1 C1 D1 1 2 4 5 9 10 12 13 LOGIC SYMBOL (IEEE/IEC) FUNCTION TABLE NOTES: H = High voltage level L = Low voltage level X = Don't care SA00352 1 & 6 2 4 v. 8 5


OCR Scan
PDF 74LVT20 SA00351 SQT402-1 MO-153 7110fl2b 74LVT20 74LVT20D 74LVT20PW
74AC125

Abstract: 74ACT125 IEC134 MS-012AB SSOP14
Text: ISSUE DATE IEC JEDEC EIAJ SQT402-1 MO-153 94-07-12 95-04-04 1997 May 15 11 Powered by , voltage level L = LOW voltage level X = don't care Z = high impedance OFF-state LOGIC SYMBOL 2 1A ^ 1Y 3 1 , 500 mW NOTES: 1 . Stresses beyond those listed may cause permanent damage to the device. These are , |N = VCc, gnd Vout = Vcc, gnd 5.5 ±2.5 H.A 'old2 Dynamic output current2 V0ld = 1 -65V max 5.5 75 , °r GND 5.5 40 H.A NOTES: 1 . All outputs loaded 2. Maximum test duration 2.0 ms; one output loaded


OCR Scan
PDF 74AC125 74ACT125 SQT402-1 MO-153 IEC134 MS-012AB SSOP14
Not Available

Abstract: No abstract text available
Text: 74ABT08PW DH DWG NUMBER SOT27- 1 SOT108- 1 SOT337- 1 SQT402-1 1995 Sep 18 98 853-1806 15752 , PIN DESCRIPTION ma PIN NUMBER 1 ,2 ,4 , 5, 9, 1 0, 1 2,13 SYMBOL An-Bn Yn GND v cc NAME AND , W - 51 v cc 13) B3 A3 TT| Y3 B2 1 ] T ] SA00342 A2 V2 3, 6, 8, 11 7 14 BO ¡ T YO [ 3" A1 [7 LOGIC SYMBOL (IEEE/IEC) B1 [ T Y1 [ ? GND ( 7 LOGIC SYMBOL_ 1 2 4 5 9 10 , DC input voltage3 CONDITIONS V |< 0 RATING -0 .5 to +7.0 - 1 8 - 1 .2 to +7.0 UNIT V mA V


OCR Scan
PDF 74ABT08 SA00342 74ABT 500ns
Not Available

Abstract: No abstract text available
Text: ; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 I I I I I 5 mm I scale DIMENSIONS (mm , interlead protrusio n s of 0.25 mm m axim um per side are n ot included. OUTLINE VERSION SQT402-1 , delay nA, nB to nY Input capacitance Power dissipation capacitance per gate See Notes 1 and 2 CONDITIONS C L = 15 pF; V CC = 3.3 V TYPICAL 6 3.5 22 UNIT ns PF PF NOTES: 1 . CpQ is used to determine the , 74LV02 DB 74LV02PW DH PKG. DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 ,4


OCR Scan
PDF 74LV02 74LV02 74HC/HCT02.
Not Available

Abstract: No abstract text available
Text: small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 I I I I I 5 mm , included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 EIAJ EUROPEAN PROJECTION , (output V oh undershoot) > 2V @ V c c = 3.3V, "Tamb = 25°C · O utput capability: standard · 1 0 Q category , 0V; Tgmb = 25°C; t r =tf < 2 .5 ns SYM BO L tpHL^PLH C| C PD PARAMETER L O co Il Il o - 1 o o > Propagation delay nA, nB, nC, nD to nY Input capacitance Power dissipation capacitance per gate Notes 1 and 2


OCR Scan
PDF 74LV20 74LV20 74HC/HCT20.
Not Available

Abstract: No abstract text available
Text: TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I , mm m axim um per side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O , DATA GND = 0V; Tgmb = 25°C; t r =tf < 2 .5 ns SYM BO L tpZL^PLZ C| C PD PARAMETER L O co Il Il o - 1 o o > Propagation delay nA, nB to nY Input capacitance Power dissipation capacitance per gate Notes 1 , 2 CO NDITIONS TYPICAL 8 3.5 4 UNIT ns PF PF NOTES: 1 Cpo is used to determ ine the dynam ic power


OCR Scan
PDF 74LV03 74LV03 74HC/HCT03.
Not Available

Abstract: No abstract text available
Text: TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I , mm m axim um per side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O , ohv (output V oh undershoot) > 2 V at V c c = 3.3 V, Tamb = 25°C · O utput capability: standard · 1 0 , = 3.3 V TYPICAL 10 3.5 UNIT ns PF PF See Notes 1 and 2 18 NOTES: 1 . CpQ is used to , 74LV11 DB 74LV11PW DH PKG. DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 3


OCR Scan
PDF 74LV11 74LV11 74HC/HCT11. 74LV1tors
Not Available

Abstract: No abstract text available
Text: width 4.4 mm SQT402-1 0 1 I I I I 2.5 I I I I I 5 mm I scale DIMENSIONS (mm are the , interlead protrusio n s of 0.25 mm m axim um per side are n ot included. OUTLINE VERSION SQT402-1 , Product specification Quad 2-input AND gate 74LV08 FEATURES · Wide operating voltage- 1 0 to 5 5 , nY Input capacitance Power dissipation capacitance per gate See Notes 1 and 2 CONDITIONS CL = 15 pF; VCC = 3.3 V TYPICAL 7 3.5 10 UNIT ns PF PF NOTES: 1 . Cpo is used to determine the dynamic power


OCR Scan
PDF 74LV08 74LV08 74HC/HCT08.
Not Available

Abstract: No abstract text available
Text: : plastic thin shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 , axim um per side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 , Input capacitance Power dissipation capacitance per gate See Notes 1 and 2 CONDITIONS CL = 15 pF; V CC = 3.3 V TYPICAL 9 3.5 12 UNIT ns PF PF NOTES: 1 . Cpo is used to determine the dynamic power , . DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 3, 9 2, 4, 10 7 12, 6, 8


OCR Scan
PDF 74LV10 74LV10 74HC/HCT10.
TAG L0 220

Abstract: No abstract text available
Text: shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 I I I I I , included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 EIAJ EUROPEAN PROJECTION , ; V CC = 3.3 V TYPICAL 6 3.5 UNIT ns PF PF See Notes NO TAG and 2 21 NOTES: 1 . CpQ is , AM ERICA 74LV04 N 74LV04 D 74LV04 DB 74LV04PW DH PKG. DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 3, 5, 9, 11, 13 2, 4, 6, 7 14 8, FUNCTION TABLE FUNCTION Data


OCR Scan
PDF 74LV04 74LV04 74HC/HCT04. TAG L0 220
74LV393PW

Abstract: No abstract text available
Text: small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I I I 2.5 I I I I I 5 mm , included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 EIAJ EUROPEAN PROJECTION , aster reset ( 1 MR, 2MR) inputs to each counter. The operation of each half of the " 3 93" is the same as , each 4-bit counter identified by the " 1 " and " 2 " in the pin description. A HIGH level on the nMR , < 2 .5 ns SYM BO L PARAMETER Propagation delay nCP to nQo nQ to nQn+ 1 nM R to nQn M aximum clock


OCR Scan
PDF 74LV393 74LV393 74HC/HCT393. 74LV393PW
Not Available

Abstract: No abstract text available
Text: TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 0 1 I I , axim um per side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O -153 , Propagation delay nA, nB, nC to nY Input capacitance Power dissipation capacitance per gate See Notes 1 and 2 CONDITIONS C L = 15 pF; V CC = 3.3 V TYPICAL 8 3.5 24 UNIT ns PF PF NOTES: 1 . Cpo is used to determine the , 74LV27PW DH PKG. DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 3, 9 2, 4, 10


OCR Scan
PDF 74LV27 74LV27
6 pin 2D 1002

Abstract: 74LV74 2d 1002 6 pin 74LV74PW 2D 1002
Text: 74LV74 N SOT27- 1 14-Pin Plastic SO -40°C to +125°C 74LV74 D 74LV74 D SOT108- 1 14-Pin Plastic SSOP Type II -40°C to +125°C 74LV74 DB 74LV74 DB SOT337- 1 14-Pin Plastic TSSOP Type I -40°C to +125°C 74LV74 PW 74LV74PW DH SQT402-1 PIN DESCRIPTION FUNCTION TABLE PIN NUMBER SYMBOL FUNCTION 1 , 13 1 RD, 2Rd , EUROPEAN PROJECTION ISSUE DATE IEC JEDEC EIAJ SQT402-1 MO-153 94-07-12 95-04-04 1998 Apr 20 11 , capacitance per flip-flop Notes 1 and 2 24 PF NOTES: 1 . Cpo is used to determine the dynamic power dissipation


OCR Scan
PDF 74LV74 74HC/HCT74. SQT402-1 MO-153 6 pin 2D 1002 2d 1002 6 pin 74LV74PW 2D 1002
74LVC04A

Abstract: 74LVC04APW MS-012AB SSOP14
Text: ISSUE DATE IEC JEDEC EIAJ SQT402-1 MO-153 94-07-12 95-04-04 1997 Jun 30 This Material , capacitance per gate Notes 1 and 2 25 PF NOTES: 1 . Cpo is used to determine the dynamic power dissipation , 74LVC04A D SOT108- 1 14-Pin Plastic SSOP Type II -40°C to +85°C 74LVC04A DB 74LVC04A DB SOT337- 1 14-Pin Plastic TSSOP Type I -40°C to +85°C 74LVC04A PW 74LVC04APW DH SOT402- 1 PIN CONFIGURATION 1Y 2A 2Y 3A , NAME AND FUNCTION 1 , 3, 5, 9, 11, 13 1A to 6A Data inputs 2, 4, 6, 8, 10, 12 1Y to 6Y Data outputs 7


OCR Scan
PDF 74LVC04A 74LVC04A SQT402-1 MO-153 74LVC04APW MS-012AB SSOP14
SV008

Abstract: No abstract text available
Text: -State) 74LV126 TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SQT402-1 , mm m axim um per side are n ot included. OUTLINE VERSION SQT402-1 REFERENCES IEC JEDEC M O , ; V| = GND to V CC1 CONDITIONS C L = 15 pF; V CC = 3.3 V TYPICAL 9 3.5 23 UNIT ns PF PF NOTE: 1 , 74LV126 DB 74LV126PW DH PKG. DWG. # SOT27- 1 SOT108- 1 SOT337- 1 SOT4Q2- 1 PIN DESCRIPTION PIN NUM BER 1 , 4, 10, 13 2, 5, 9, 12 3, 6, 8, 11 7 14 SYM BO L 1 0 E -4 0 E 1 A -4 A 1 Y -4 Y GND V CC FUNCTION


OCR Scan
PDF 74LV126 74LV126 SV008
Supplyframe Tracking Pixel