SN74LVC74AD Search Results

LC74A

Contextual Info: SN54LVC74A, SN74LVC74A www.ti.com SCAS287T – JANUARY 1993 – REVISED JULY 2013 DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET Check for Samples: SN54LVC74A, SN74LVC74A FEATURES DESCRIPTION • • • • The SN54LVC74A dual positive-edge-triggered Dtype flip-flop is designed for 2.7-V to 3.6-V VCC

lc74a

Abstract: A115-A C101 SN54LVC74A SN74LVC74A lvc74a
Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287P – JANUARY 1993 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q

smd transistor 43t

Abstract: on line ups circuit schematic diagram capacitor 103 .01uf SMPTE274 2d2 smd transistor THS8134 AMP 103309-1 1080i field pattern black EPM7128SLC84-7 SMD G8
Contextual Info: THS8133/34 EVM User’s Guide September 1999 Mixed Signal Products SLVU020A IMPORTANT NOTICE Texas Instruments and its subsidiaries TI reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information

5555 FAIRCHILD optocoupler

Abstract: MC74HC374N 74hc14n equivalent NC7S125M5 14069 HCF4541BEY APPLICATION HCF4013BE 4026 fairchild datasheet 14543 motorola Motorola DM74LS139N
Contextual Info: R E L I A B L E . L O G I C . I N N O V A T I O N . Logic Cross-Reference Logic Cross-Reference 2003 Texas Instruments Printed in the U.S.A. by Texoma Business Forms, Durant, Oklahoma Printed on recycled paper. SCYB017A NEW First Revision Logic Cross-Reference

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

LCV74A

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287M – JANUARY 1993 – REVISED MARCH 2002 D 1CLR 1D 1CLK 1PRE 1Q 1Q GND 1 14 2 13 3 12 4 11 5 10 6 9 7 8 VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

LCV74A

Abstract: LVC74A
Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287N – JANUARY 1993 – REVISED JULY 2002 D D SN54LVC74A . . . J OR W PACKAGE SN74LVC74A . . . D, DB, NS, OR PW PACKAGE TOP VIEW 1CLR 1D 1CLK 1PRE 1Q 1Q GND

HDR1X3

Abstract: BLM-21A102S S2-AES17LP
Contextual Info: CDB43L42 Evaluation Board for CS43L42 Rev. D Features Description l Demonstrates The CDB43L42 evaluation board is an excellent means for quickly evaluating the CS43L42 24-bit, stereo D/A converter. Evaluation requires an analog signal analyzer, a digital signal source, a PC for controlling the

LC74A

Abstract: SN74LVC74ADT A115-A C101 SN54LVC74A SN74LVC74A
Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS287S − JANUARY 1993 − REVISED AUGUST 2004 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q

schematic diagram atx Power supply 500w

Abstract: pioneer PAL 012A 1000w inverter PURE SINE WAVE schematic diagram 600va numeric ups circuit diagrams winbond bios 25064 TLE 9180 infineon smsc MEC 1300 nu TBE schematic diagram inverter 2000w DK55 circuit diagram of luminous 600va UPS
Contextual Info: QUICK INDEX NEW IN THIS ISSUE! Detailed Index - See Pages 3-24 Digital Signal Processors, iCoupler , iMEMS® and iSensor . . . . . 805, 2707, 2768-2769 Connectors, Cable Assemblies, IC Sockets . . . . . . . . . . . 28-568 RF Connectors . . . . . . . . . . . . . . . . . . . . . . Pages 454-455

Arduino Mega2560

Abstract: 13001 S 6D TRANSISTOR arduino uno rev 3 agilent optical encoder 9988 MZ 13001 TRANSISTOR arduino mega 2650 skiip 613 gb 123 ct arduino sound sensor module pic arduino nano mc34063l
Contextual Info: ND3% BASE1 XXXX2108-0010-1-P 10 TSQ: 3001 CMS: CMS-USM TS host OP: NN COMP: 15-07-11 Hour: 13:07 TS:TS date TS time MCUS, MPUS, DSPS & DEVELOPMENT TOOLS Find Datasheets Online 8-BIT MCUS & DEVELOPMENT TOOLS 1 PSoC 3 DEVELOPMENT KITS ARDUINO MCU DEVLOPMENT PLATFORM

LVC74

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET SCAS287P – JANUARY 1993 – REVISED SEPTEMBER 2002 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 14 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

R228

Abstract: C274 R226 R239 R22-6 R238 R283 SN74LVC74ADB DO3316P-223 LTC1265
Contextual Info: 4 S17 minispdt S18 POWER_SIGS 1 1 minispdt 3 2 3 2 PWR_EN RP2 4.7k 3.3V 16 11 11 6 5 10 4 2 3 The LTC1265CS requires many special printed circuit board layout rules. They may be obtained by CT ITH SGND PWR_EN nRESET VDD_FAULT U15 LTC1265 BPWR_EN PWR_EN PO_RST#

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

lc74a

Abstract: A115-A C101 SN54LVC74A SN74LVC74A
Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVEĆEDGEĆTRIGGERED DĆTYPE FLIPĆFLOPS WITH CLEAR AND PRESET SCAS287R − JANUARY 1993 − REVISED MARCH 2004 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 2 13 2CLR 3 12 2D 4 11 2CLK 5 10 2PRE 9 2Q 6 7 8 1CLK NC 1PRE NC 1Q 3

Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE

LC74A

Abstract: A115-A C101 SN54LVC74A SN74LVC74A
Contextual Info: SN54LVC74A, SN74LVC74A DUAL POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOPS WITH CLEAR AND PRESET www.ti.com SCAS287S – JANUARY 1993 – REVISED MAY 2005 • 3 12 4 11 5 10 6 9 7 8 1D 1CLK 1PRE 1Q 1Q 1 14 1D VCC 2CLR 2D 2CLK 2PRE 2Q 2Q SN54LVC74A . . . FK PACKAGE