SCES345 Search Results

A115-A

Abstract: C101 SN54LV11A SN74LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

A115-A

Abstract: C101 SN54LV11A SN74LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

A115-A

Abstract: C101 SN54LV11A SN74LV11A lv11a
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345 – DECEMBER 2000 D D D D D SN54LV11A . . . J OR W PACKAGE SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce) <0.8 V at VCC= 3.3 V, TA = 25°C

A115-A

Abstract: C101 SN54LV11A SN74LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 D D D D D SN54LV11A . . . J OR W PACKAGE SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

A115-A

Abstract: C101 SN54LV11A SN74LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345B – DECEMBER 2000 – REVISED JULY 2003 D D D D D 2-V to 5.5-V VCC Operation Max tpd of 7 ns at 5 V Typical VOLP Output Ground Bounce <0.8 V at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot)

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

A115-A

Abstract: C101 SN54LV11A SN74LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 D D D D D SN54LV11A . . . J OR W PACKAGE SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

A115-A

Abstract: C101 SN54LV11A SN74LV11A LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3-INPUT POSITIVE-AND GATES SCES345A – DECEMBER 2000 – REVISED JULY 2001 D D D D D SN54LV11A . . . J OR W PACKAGE SN74LV11A . . . D, DB, DGV, NS, OR PW PACKAGE TOP VIEW 2-V to 5.5-V VCC Operation Typical VOLP (Output Ground Bounce)

A115-A

Abstract: C101 SN54LV11A SN74LV11A
Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345C − DECEMBER 2000 − REVISED DECEMBER 2004 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

Contextual Info: SN54LV11A, SN74LV11A TRIPLE 3ĆINPUT POSITIVEĆAND GATES SCES345D − DECEMBER 2000 − REVISED APRIL 2005 D 2-V to 5.5-V VCC Operation D Max tpd of 7 ns at 5 V D Typical VOLP Output Ground Bounce D D D D 1A 1B 2A 2B 2C 2Y GND <0.8 V at VCC = 3.3 V, TA = 25°C

PLL WITH VCO 4046 appli note philips

Abstract: CD74HC4050 marking microstar ms 4011 CI 40106 8952 microcontroller ic 4017 decade counter datasheet ic HC 4066 AG GK 7002 7 SEGMENT DISPLAY LT 543 PIN CONFIGURATION LA 4508 as af power amplifier
Contextual Info: LOGIC OVERVIEW 1 PRODUCT INDEX 2 FUNCTIONAL CROSS−REFERENCE 3 DEVICE SELECTION GUIDE 4 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE FIRST HALF 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,

74LS series logic gates 3 input or gate

Abstract: sn74 series TTL logic gates list 4017 counter IC datasheet data sheet ic 4017 IC CD 4033 pin configuration CMOS Data Book Texas Instruments Incorporated 74LS series logic gates hp 4514 TEXAS INSTRUMENTS SN7400 SERIES ic 4026 down counter
Contextual Info: LOGIC OVERVIEW 1 FOCUS ON THE IDEAL LITTLE LOGIC SOLUTION 2 FUNCTIONAL INDEX 3 FUNCTIONAL CROSSĆREFERENCE 4 DEVICE SELECTION GUIDE 5 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE FIRST HALF 2002 IMPORTANT NOTICE

hp laptop MOTHERBOARD pcb CIRCUIT diagram

Abstract: hp laptop battery pack pinout SCBD002C hp laptop battery pinout sn74154 SN74LVC1G373 SDFD001B 4052 IC circuit diagram lg crt monitor circuit diagram PLL CD 4046
Contextual Info: LOGIC OVERVIEW 1 PRODUCT INDEX 2 FUNCTIONAL CROSS−REFERENCE 3 DEVICE SELECTION GUIDE 4 PACKAGING AND MARKING INFORMATION A LOGIC PURCHASING TOOL/ALTERNATE SOURCES B LOGIC SELECTION GUIDE SECOND HALF 2004 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,