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SCAS614A Equivalents

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SCAS614A Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4	PDF
48-PIN Abstract: CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A CDC318ADL CDC318ADLG4 CDC318ADLR	PDF
K3638 Abstract: 4Y04 Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin K3638 4Y04	PDF
48-PIN Abstract: CDC318A Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A	PDF
k3638 Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin k3638	PDF
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin	PDF
48-PIN Abstract: CDC318A Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A	PDF
48-PIN Abstract: CDC318A Contextual Info: CDC318A 1-LINE TO 18-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A – SEPTEMBER 1998 – REVISED JUNE 2002 D D D D D D D D D D DL PACKAGE TOP VIEW High-Speed, Low-Skew 1-to-18 Clock Buffer for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18-LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin CDC318A	PDF
Contextual Info: CDC318A 1ĆLINE TO 18ĆLINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS614A − SEPTEMBER 1998 − REVISED JUNE 2002 D High-Speed, Low-Skew 1-to-18 Clock Buffer D D D D D D D D D DL PACKAGE TOP VIEW for Synchronous DRAM (SDRAM) Clock Buffering Applications	Original	CDC318A 18LINE SCAS614A 1-to-18 100-MHz MIL-STD-883, 48-Pin	PDF