CDC319
Abstract: CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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cdc31910-linescas590a1-to-10+7mil-std-88328-pincdc319dbcdc319dbg4cdc319dbrcdc319dbrg4mo-150
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CDC319
Abstract: MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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cdc31910-linescas590a1-to-10+3mil-std-88328-pinmo-150
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CDC319
Abstract: CDC319DB CDC319DBG4 CDC319DBR CDC319DBRG4 MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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cdc31910-linescas590a1-to-10+7mil-std-88328-pincdc319dbcdc319dbg4cdc319dbrcdc319dbrg4mo-150
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PDF
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CDC319
Abstract: CDC319DB CDC319DBR CDC319DBRG4 MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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cdc31910-linescas590a1-to-10+6mil-std-88328-pincdc319dbcdc319dbrcdc319dbrg4mo-150
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Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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cdc31910-linescas590a1-to-10+2mil-std-88328-pin
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PDF
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Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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cdc31910-linescas590a1-to-10+2mil-std-88328-pin
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PDF
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CDC319
Abstract: MO-150
Contextual Info: CDC319 1-LINE TO 10-LINE CLOCK DRIVER WITH I2C CONTROL INTERFACE SCAS590A – DECEMBER 1997 – REVISED OCTOBER 2001 D D D D D D D D D High-Speed, Low-Skew 1-to-10 Clock Buffer for SDRAM Synchronous DRAM Clock Buffering Applications Output Skew, tsk(o), Less Than 250 ps
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Original
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cdc31910-linescas590a1-to-10+3mil-std-88328-pinmo-150
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PDF
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