SCAS14 Search Results

Contextual Info: SN74ACT2235 1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148E - DECEMBER 1990 - REVISED APRIL 1998 • Independent Asynchronous Inputs and Outputs • Access Times of 25 ns With a 50-pF Load • Data Rates up to 50 MHz • Low-Power Advanced CMOS Technology

Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

Contextual Info: SN74ACT2236 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS149A- APRIL 1990 - REVISED SEPTEMBER 1995 I n d e p e n d e n t A s y n c h r o n o u s I nput s and Outputs A c c e s s T i m e s o f 2 5 ns With a 5 0 -pF Load L o w - P o w e r A d v a n c e d C M O S T e c hn o l o g y

Contextual Info: 74ACT11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS14 5 -D3435, MARCH 1990-REVISEDAPRIL 1993 * Inputs Are TTL-Voltage Compatible DW OR N PACKAGE TOP VIEW * Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators * Fully-Buffered Outputs for Maximum

74ACT11014

Contextual Info: 74ACT11014 HEX SCHMITT-TRIGGER INVERTER SCAS142B – FEBRUARY 1991 – REVISED AUGUST 1995 D D D D D D DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

SN74ACT2235

Abstract: SN74ACT2236
Contextual Info: SN74ACT2236 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS149A – APRIL 1990 – REVISED SEPTEMBER 1995 D D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional 1024 Words by 9 Bits Each

Contextual Info: 54AC11014, 74AC11014 HEX SCHMITT-TRIGGER INVERTERS SCAS141A – AUGUST 1989 – REVISED AUGUST 1995 D D D D D Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise EPIC  Enhanced-Performance Implanted

74ACT11014

Abstract: 74ACT11014DW 74ACT11014N
Contextual Info: 74ACT11014 HEX SCHMITT-TRIGGER INVERTER SCAS142B – FEBRUARY 1991 – REVISED AUGUST 1995 D D D D D D DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

SCAS144

Contextual Info: 74ACT11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCAS144 – OCTOBER 1990 – REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs

Contextual Info: 74ACT11898 10ĆBIT PARALLELĆOUT SERIAL SHIFT REGISTER ą ą SCAS144 − OCTOBER 1990 − REVISED APRIL 1993 • • • • • • • • • • DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs

Contextual Info: 54AC11014, 74AC11014 HEX SCHMITTĆTRIGGER INVERTERS SCAS141A − AUGUST 1989 − REVISED AUGUST 1995 54AC11014 . . . J OR W PACKAGE 74AC11014 . . . DW OR N PACKAGE TOP VIEW D Flow-Through Architecture Optimizes D D D D PCB Layout Center-Pin VCC and GND Configurations

Contextual Info: 74ACT11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS145 – D3435, MARCH 1990 – REVISED APRIL 1993 • • • • • • • • Inputs Are TTL-Voltage Compatible Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Fully-Buffered Outputs for Maximum

Contextual Info: 74AC11898 10-BIT PARALLEL-OUT SERIAL SHIFT REGISTER SCAS143 – OCTOBER 1990 – REVISED APRIL 1993 • • • • • • • • • DW OR N PACKAGE TOP VIEW AND-Gated (Enable/Disable) Serial Inputs Fully Buffered Clock and Serial Inputs Direct Clear

MS-018

Abstract: SN74ACT2235
Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

74ACT11014

Contextual Info: 74ACT11014 HEX SCHMITT-TRIGGER INVERTER SCAS142B – FEBRUARY 1991 – REVISED AUGUST 1995 D D D D D D DW OR N PACKAGE TOP VIEW Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin VCC and GND Configurations Minimize High-Speed Switching Noise

74AC11174

Contextual Info: 74AC11174 HEX D-TYPE FLIP-FLOP WITH CLEAR SCAS146 – MARCH 1990 – REVISED APRIL 1993 • • • • • • DW OR N PACKAGE TOP VIEW Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture Optimizes

74ACT11174

Abstract: 74ACT11174DW 74ACT11174DWR 74ACT11174N
Contextual Info: 74ACT11174 HEX DĆTYPE FLIPĆFLOP WITH CLEAR ą ą SCAS145 − D3435, MARCH 1990 − REVISED APRIL 1993 • • • • • • • • Inputs Are TTL-Voltage Compatible Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Fully-Buffered Outputs for Maximum

74ACT11014

Contextual Info: 74ACT11014 HEX SCHMITTĆTRIGGER INVERTER SCAS142B − FEBRUARY 1991 − REVISED AUGUST 1995 D Inputs Are TTL-Voltage Compatible D Flow-Through Architecture Optimizes DW OR N PACKAGE TOP VIEW PCB Layout 1Y 2Y 3Y GND GND GND GND 4Y 5Y 6Y D Center-Pin VCC and GND Configurations

SN74ACT2235

Abstract: SN74ACT2235-20FN SN74ACT2235-20PAG SN74ACT2235-20PM
Contextual Info: SN74ACT2235 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148F – DECEMBER 1990 – REVISED JUNE 2003 D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional Dual 1024 by 9 Bits

af b7

Abstract: SN74ACT2235 SN74ACT2236
Contextual Info: SN74ACT2236 1024 x 9 × 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS149A – APRIL 1990 – REVISED SEPTEMBER 1995 D D D D D D D D D D D D Independent Asynchronous Inputs and Outputs Low-Power Advanced CMOS Technology Bidirectional 1024 Words by 9 Bits Each

Contextual Info: 74ACT11174 HEX DĆTYPE FLIPĆFLOP WITH CLEAR ą ą SCAS145 − D3435, MARCH 1990 − REVISED APRIL 1993 • • • • • • • • Inputs Are TTL-Voltage Compatible Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Fully-Buffered Outputs for Maximum

74AC11174

Contextual Info: 74AC11174 HEX DĆTYPE FLIPĆFLOP WITH CLEAR ą ą SCAS146 − MARCH 1990 − REVISED APRIL 1993 • • • • • • DW OR N PACKAGE TOP VIEW Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Flow-Through Architecture Optimizes

Contextual Info: 74ACT11174 HEX DĆTYPE FLIPĆFLOP WITH CLEAR ą ą SCAS145 − D3435, MARCH 1990 − REVISED APRIL 1993 • • • • • • • • Inputs Are TTL-Voltage Compatible Applications Include: Buffer/Storage Registers, Shift Registers, Pattern Generators Fully-Buffered Outputs for Maximum

Texas Instruments TTL handbook

Abstract: D1044 SN74ACT2235 SN74ACT2236
Contextual Info: SN74ACT2235 1024 x 9 x 2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCAS148C - DECEMBER 1990 - REVISED SEPTEMBER 1995 • Independent Asynchronous Inputs and Outputs • Low-Power Advanced CMOS Technology • Bidirectional GND FN PACKAGE TO P VIEW