SCAA055 Search Results

propagationdelay

Abstract: SCAA055 JESD65 SLLA075 SCAD004B
Contextual Info: Application Report SCAA055 – November 2001 Defining Skew, Propagation-Delay, Phase Offset Phase Error High Performance Analog/CDC Kal Mustafa ABSTRACT This application note discusses various types of skew, propagation delays, and phase error/phase offset in general. Special attention is given to important parameters that are

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

c.i 9409

Contextual Info: CDC339 CLOCK DRIVER WITH 3-STATE OUTPUTS SCAS331 – DECEMBER 1992 – REVISED MARCH 1994 D D D D D D D DB OR DW PACKAGE TOP VIEW Low Output Skew, Low Pulse Skew for Clock-Distribution and Clock-Generation Applications TTL-Compatible Inputs and Outputs Distributes One Clock Input to Eight

Contextual Info: CDCV850, CDCV850I 2.5ĆV PHASE LOCK LOOP CLOCK DRIVER WITH 2ĆLINE SERIAL INTERFACE SCAS647B – OCTOBER 2000 – REVISED DECEMBER 2002 D Phase-Lock Loop Clock Driver for Double D D D D D D D D D Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible

Contextual Info: CDC857-2, CDC857-3 2.5-/3.3-V PHASE-LOCK LOOP CLOCK DRIVERS SCAS627A – SEPTEMBER 1999 – DECEMBER 1999 D D D D D D Phase-Lock Loop Clock Distribution for Double Data Rate Synchronous DRAM Applications Distributes One Differential Clock Input to Ten Differential Outputs

Contextual Info: CDCV857B 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS676 – JUNE 2002 D Phase-Lock Loop Clock Driver for Double D D D D D description GND Y0 Y0 VDDQ Y1 Y1 GND GND Y2 Y2 VDDQ VDDQ CLK CLK VDDQ AVDD AGND GND Y3 Y3 VDDQ Y4 Y4 GND 1 48 2 47 3 46 4 45 5 44 6 43 7 42

INSSTE32882

Abstract: maxim dallas 2501 P16CV SY100EL16 SN65MLVD201 SN65EPT22 INCU877 INCUA877 ttl crystal oscillator using 7404 P16CV857B
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

PC133 registered reference design

Contextual Info: CDCF2510 3.3-V PHASE-LOCK LOOP CLOCK DRIVER SCAS628C – APRIL 1999 – REVISED MARCH 2001 D D D D D D D D D D D D D PW PACKAGE TOP VIEW Designed to Meet PC133 SDRAM Registered DIMM Specification Rev. 0.9 Spread Spectrum Clock Compatible Operating Frequency 25 MHz to 140 MHz

MUX21

Contextual Info: CDC7005 3.3-V HIGH PERFORMANCE CLOCK SYNCHRONIZER AND JITTER CLEANER SCAS685A – DECEMBER 2002 – REVISED FEBRUARY 2003 D High Performance 1:5 PLL Clock TERMINAL ASSIGNMENTS TOP VIEW Synchronizer D Two Clock Inputs: VCXO_IN Clock Is D D D D D D D D D D

DALLAS 2501

Abstract: CDC2509 TSSOP-56 footprint texas 14 pin ic 7404 datasheet SN65MLVD201 pll dip 546 spi mux CDCVF25084 TTL 7404 TBA 950 2x
Contextual Info: R E A L W O R L D S I G N A L P TM R O C E S S I N G Clocks and Timing Selection Guide 4Q 2003 Table of Contents Overview Clock Distribution Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4

CDCVF111

Abstract: MS-018 SCAA055 SCAA056
Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

Contextual Info: CDCVF25081 3.3-V PHASED-LOCK LOOP CLOCK DRIVER SCAS671 – OCTOBER 2001 D Phase-Locked Loop-Based Zero-Delay D PACKAGE SOIC PW PACKAGE (TSSOP) (TOP VIEW) Buffer D Operating Frequency: 10 MHz to 200 MHz D Low Jitter (Cycle-Cycle): ±100 ps Over the D D D

k2228

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

INSSTE32882

Abstract: maxim dallas 2501 insstua32866 INSSTU32864 INSSTU32866 ttl crystal oscillator using CIRCUIT DIAGRAM INCUA877 ps 2501 dallas GSM home automation block diagram INCU877
Contextual Info: Clocks and Timing Guide www.ti.com/clocks 2Q 2009 2 Clocks and Timing Guide ➔ Clocks and Timing Selection Tree Clocks by Function Clock Distribution Non- PLL Fanout Buffers PLL Buffers RF Synthesizers Clock Generation General Purpose Generator/Synthesizer

SCAA055

Abstract: CDCVF111 CDCVF111FN CDCVF111FNR MS-018 SCAA056
Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

Contextual Info: CDCV855, CDCV855I 2.5-V PHASE-LOCK LOOP CLOCK DRIVER SCAS660A – SEPTEMBER 2001 – REVISED DECEMBER 2002 D Phase-Lock Loop Clock Driver for Double D D D D D D D D D PW PACKAGE TOP VIEW Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

SCAA048

Contextual Info: CDCV857A 2.5-V PHASE LOCK LOOP CLOCK DRIVER SCAS667A – APRIL 2001 – REVISED AUGUST 2002 D D D D D Phase-Lock Loop Clock Driver for Double Data-Rate Synchronous DRAM Applications Spread Spectrum Clock Compatible Operating Frequency: 60 to 180 MHz Low Jitter cyc–cyc : ±50 ps

Contextual Info: CDCVF2310 2.5-V TO 3.3-V HIGH PERFORMANCE CLOCK BUFFER SCAS666A – JUNE 2001 – REVISED AUGUST 2002 D High Performance 1:10 Clock Driver for D D D D D D D General Purpose Applications. Operates up to 200 MHz at VDD 3.3 V Pin-to-Pin Skew < 100 ps at VDD 3.3 V

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

Contextual Info: CDCVF111 1:9 DIFFERENTIAL LVPECL CLOCK DRIVER SCAS670B – SEPTEMBER 2001 – REVISED JUNE 2002 D Low-Output Skew for Clock-Distribution FN PACKAGE TOP VIEW Applications D D (LVPECL) Compatible Inputs and Outputs Distributes Differential Clock Inputs to Nine

schematic diagram 48v dc convertor tl3845

Abstract: sg3524 spice model for pspice schematic diagram 48v ac regulator uc3842 schematic diagram inverter 12v to 24v 30a audio Amp. mosfet 1000 watt 24v dc motor speed control lm324 mini-LVDS and TFT-LCD Timing Controller sg3524 spice model UC1825 spice 500 watt power circuit diagram uc3825
Contextual Info: Selection Guide EIGHTH EDITION Analog/Mixed-Signal Products Designer’s Master Selection Guide August 2002 1996, 1997, 1999, 2000, 2001, 2002 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries TI reserve the right to make corrections, modifications,