PL310 Search Results

HP16092A

Abstract: HP4191A PL3109CA
Contextual Info: SPECIFICATION CUSTOMER: ITEM: CUST.P/N: K.C.P/N: A5 FS 31x5x12-1.0 1 SHAPE : (2)ELECTRICAL REQUIREMENTS: Z 1= 25 -0 OHM AT 25 MHz Z 2= 49 -0 OHM AT PL3109CA A 31±1.0 m/m B 5±0.3 m/m C 12±0.5 m/m D 27±0.7 m/m E 1.0±0.2 m/m F m/m G m/m (3) TEST CONDITIONS:

thurlby pl320

Abstract: thurlby pl310 PL330QMD PL320QMD PL330TP PL154 PL310 PL320 PL320QMT PL310QMD
Contextual Info: CYAN MAGENTA YELLOW BLACK Technical Specifications Technical Specifications continued MODEL SELECTOR GUIDE MAIN OUTPUT S Output Range: MODEL MAIN OUTPUT(S) LOGIC OUTPUT INTERFACES GPIB PL310 0 - 32V at 0 - 1A PL320 0 - 32V at 0 - 2A PL154 0 - 15.5V at 0 - 4A

thurlby pl320

Abstract: thurlby pl310 PL320 PL330QMD 600va ups Thurlby PL320QMD PL330P PL310 PL154
Contextual Info: Technical Specifications Technical Specifications continued MODEL SELECTOR GUIDE MAIN OUTPUT S Out put Range: MODEL MAIN OUT PUT(S) PL310 0 - 32V at 0 - 1A PL320 0 - 32V at 0 - 2A PL154 0 - 15.5V at 0 - 4A PL330 0 - 32V at 0 - 3A PL310QMD 2 x 0 - 32V at 0 - 1A

PD280 potentiometer

Abstract: C 2575 PL300 PD2310 300 348 PL310
Contextual Info: Winkelsensoren potentiometrisch Rotary Sensors potentiometric Baureihe Series GL W AL P L I 30, PL240, PL300, PL310 Messbereich Efectrcal angle 150.354 0 340 s 300. .348 • Gehäusegröße Housing size 0 3 1 .7 4 m m 0 32 m m 0 13.22.2 m m Unabhängige Linearität

PL310

Abstract: Cortex A9 instruction set arm cortex a9 mpcore B13AC primecell pl310 PL310 application note ARM Cortex A15 ARMv7 Architecture Reference Manual cortex a9 CORTEX-A9
Contextual Info: PrimeCell Level 2 Cache Controller PL310 Revision: r2p0 Technical Reference Manual Copyright 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0246C PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual Copyright © 2007, 2008 ARM Limited. All rights reserved.

PL310

Abstract: tcm 2911 TrustZone PL310 TECHNICAL MANUAL ARMv7 Architecture Reference Manual
Contextual Info: PL310 Cache Controller Revision: r0p0 Technical Reference Manual Copyright 2007 ARM Limited. All rights reserved. ARM DDI 0246A PL310 Cache Controller Technical Reference Manual Copyright © 2007 ARM Limited. All rights reserved. Release Information Change history

ARM Cortex-A9

Abstract: PL310 TECHNICAL MANUAL 2114 ram l2 cache verilog code PL310 ARMv7 TrustZone AMBA AXI AMBA file write AXI verilog code l2 cache design in verilog
Contextual Info: PrimeCell Level 2 Cache Controller PL310 Revision: r1p0 Technical Reference Manual Copyright 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0246B PrimeCell Level 2 Cache Controller (PL310) Technical Reference Manual Copyright © 2007, 2008 ARM Limited. All rights reserved.

PL310

Abstract: IP54 SCHUTZART
Contextual Info: PL310 Elektrische Daten Anschlusswiderstand 1/5/10 kOhm Widerstandstoleranz ±20 % Unabhängige Linearität ±1 % des Messber. Elektrischer Winkel 340 ° Wiederholgenauigkeit max. 0.1 ° Temperaturkoeffizient des Spannungsteilers 50 ppm/°C Empfohlener Betriebsstrom im Schleiferkreis

SBZP

Abstract: PL310 transistor B1010 PL310 TECHNICAL MANUAL PL310 application note
Contextual Info: PrimeCell Level 2 MBIST Controller PL310 Revision: r2p0 Technical Reference Manual Copyright 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402C PrimeCell Level 2 MBIST Controller (PL310) Technical Reference Manual Copyright © 2007, 2008 ARM Limited. All rights reserved.

l2 cache design in verilog

Abstract: PL310 PL310 TECHNICAL REFERENCE l2 cache design in verilog code q5 tag transistor B1010
Contextual Info: PrimeCell Level 2 MBIST Controller PL310 Revision: r1p0 Technical Reference Manual Copyright 2007, 2008 ARM Limited. All rights reserved. ARM DDI 0402B PrimeCell Level 2 MBIST Controller (PL310) Technical Reference Manual Copyright © 2007, 2008 ARM Limited. All rights reserved.

PL310

Abstract: PL310 TECHNICAL MANUAL q5 tag transistor B1010
Contextual Info: PL310 MBIST Controller Revision: r0p0 Technical Reference Manual Copyright 2007 ARM Limited. All rights reserved. ARM DDI 0402A PL310 MBIST Controller Technical Reference Manual Copyright © 2007 ARM Limited. All rights reserved. Release Information Change history

Sony IMX 183

Abstract: Sony sony cmos sensor imx 178 Sony imx 214 Sony ImX 252 sony cmos sensor imx 226 Sony IMX 219 CMOS Sony "IMX 219" CMOS sony IMX 322 cmos sony cmos sensor imx 185
Contextual Info: i.MX 6Solo/6DualLite Applications Processor Reference Manual Document Number: IMX6SDLRM Rev. 1, 04/2013 i.MX 6Solo/6DualLite Applications Processor Reference Manual, Rev. 1, 04/2013 2 Freescale Semiconductor, Inc. Contents Section number Title Page Chapter 1

Contextual Info: HPLR3103, HPLU3103 Data Sheet 52A, 30V, 0.019 Ohm, N-Channel Logic Level, Power MOSFETs These are N-Channel enhancement mode silicon gate power field effect transistors. They are advanced power MOSFETs designed, tested, and guaranteed to withstand a specified level of energy in the breakdown avalanche mode

Contextual Info: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per

Contextual Info: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per

tb540

Contextual Info: Surface Mount Bandpass Filter TBP-154+ ฀50Ω฀฀฀฀฀฀฀฀฀136฀to฀175฀MHz฀฀ The Big Deal •฀ Small฀size฀ 0.25"฀x฀0.25"฀x฀0.10" •฀ High฀rejection •฀ Flat฀group฀delay,฀17฀ns฀typical •฀ Broad฀band฀ilter฀(fractional฀bandwidth฀of฀25%)

Contextual Info: SPEAr1340 Dual-core Cortex A9 HMI embedded MPU Datasheet − preliminary data Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – 32+32 KB L1 caches per core, with parity check – Shared 512 KB L2 cache – Accelerator coherence port ACP

VFPv4-D16

Abstract: ARMv7 Architecture Reference Manual AT551-DC-06001 VFPv4 ARM IHI 0029 fpu coprocessor cortex-a5 VFPv3 CoreSight Architecture Specification CP15
Contextual Info: Cortex-A5 Floating-Point Unit Revision: r0p1 Technical Reference Manual Copyright 2009, 2010 ARM. All rights reserved. ARM DDI 0449B ID101810 Cortex-A5 Floating-Point Unit Technical Reference Manual Copyright © 2009, 2010 ARM. All rights reserved.

VFPv4

Abstract: cortex-a5 cortex-a5 integration manual ARMv7 Architecture Reference Manual cortex-a5 processor ARM IHI 0029 VFPv4 instruction set coresight CoreSight Architecture Specification ARMv6 Architecture Reference Manual
Contextual Info: Cortex-A5 NEON Media Processing Engine ™ Revision: r0p1 Technical Reference Manual Copyright 2009, 2010 ARM. All rights reserved. ARM DDI 0450B ID101810 Cortex-A5 NEON Media Processing Engine Technical Reference Manual Copyright © 2009, 2010 ARM. All rights reserved.

cortex a9

Abstract: Cortex A9 instruction set PL310 l2 cache verilog code l2 cache design in verilog code PL310 TECHNICAL MANUAL ARM Cortex-A9 cortex-a9 Cortex mpcore verilog code 8 bit LFSR
Contextual Info: AMBA Level 2 Cache Controller L2C-310 Revision: r3p0 Technical Reference Manual Copyright 2007-2009 ARM. All rights reserved. ARM DDI 0246D (ID110109) AMBA Level 2 Cache Controller (L2C-310) Technical Reference Manual Copyright © 2007-2009 ARM. All rights reserved.

cortex a9 specification

Abstract: Cortex A9 instruction set Dual-core ARM Cortex-A9 CPU spear1310 led matrix 16X32 china cortex a9 arm cortex a9 ARM v7 cortex a9 block diagram led matrix 16X32 axi compliant ddr3 controller
Contextual Info: SPEAr1310 Dual-core Cortex A9 embedded MPU for communications Data brief Features • CPU subsystem: – 2x ARM Cortex A9 cores, up to 600 MHz – Supporting both symmetric SMP and asymmetric (AMP) multiprocessing – 32+32 KB L1 Instructions/Data cache per

VFPv4

Abstract: cortex-a5 VFPv3 instruction set ARM IHI 0029 VFPv4 instruction set ARMv7 Architecture Reference Manual cortex-a5 integration manual ARMv6 Architecture Reference Manual ARMv7 neon ARMv7 Architecture Reference Manual NEON
Contextual Info: Cortex -A5 NEON Media Processing Engine ™ Revision: r0p0 Technical Reference Manual Copyright 2009 ARM. All rights reserved. ARM DDI 0450A ID012010 Cortex-A5 NEON Media Processing Engine Technical Reference Manual Copyright © 2009 ARM. All rights reserved.

AMBA AXI dma controller designer user guide

Abstract: cortex-a5 integration manual Jazelle v1 Architecture Reference Manual PL390 Coresight cortex-a5 CP14 CP15 "cortex a5" CORTEX-A9
Contextual Info: Cortex -A5 MPCore ™ Revision: r0p0 Technical Reference Manual Copyright 2010 ARM. All rights reserved. ARM DDI 0434A ID052910 Cortex-A5 MPCore Technical Reference Manual Copyright © 2010 ARM. All rights reserved. Release Information The following changes have been made to this book.

cortex-a5

Abstract: cortex-a5 processor arm cortex a5 mpcore arm cortex a9 mpcore Jazelle v1 Architecture Reference Manual PL390 CP15 Powered Monitor jazelle CP14 CP15
Contextual Info: Cortex-A5 MPCore ™ Revision: r0p1 Technical Reference Manual Copyright 2010 ARM. All rights reserved. ARM DDI 0434B ID101810 Cortex-A5 MPCore Technical Reference Manual Copyright © 2010 ARM. All rights reserved. Release Information The following changes have been made to this book.