MGQF011 Search Results

Contextual Info: MECHANICAL DATA MGQF011 – DECEMBER 1996 HFP S-GQFP-F132 CERAMIC QUAD FLATPACK 1.540 (39,12) SQ 1.460 (37,08) 116 84 117 83 0.025 (0,635) 1 0.014 (0,36) 0.009 (0,20) 17 51 18 50 0.800 (20,32) TYP 0.150 (3,81) 0.110 (2,79) 0.960 (24,38) SQ 0.940 (23,88)

S-GQFP-F132

Contextual Info: MECHANICAL DATA MGQF011 – DECEMBER 1996 HFP S-GQFP-F132 CERAMIC QUAD FLATPACK 1.540 (39,12) SQ 1.460 (37,08) 116 84 117 83 0.025 (0,635) 1 0.014 (0,36) 0.008 (0,20) 17 51 18 50 0.800 (20,32) TYP 0.150 (3,81) 0.110 (2,79) 0.965 (24,51) SQ 0.935 (23,75)

Contextual Info: MECHANICAL DATA MGQF011 – DECEMBER 1996 HFP S-GQFP-F132 CERAMIC QUAD FLATPACK 1.540 (39,12) SQ 1.460 (37,08) 116 84 117 83 0.025 (0,635) 1 0.014 (0,36) 0.008 (0,20) 17 51 18 50 0.800 (20,32) TYP 0.150 (3,81) 0.110 (2,79) 0.965 (24,51) SQ 0.935 (23,75)

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

5962-9560801NXD

Abstract: SN54ACT3641 SN74ACT3641 SNJ54ACT3641HFP
Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C − APRIL 1999 − REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D − Object Compatible With the TMS320C2xx Family − Source Code Compatible With

Contextual Info: SN54ACT3641 1024 x 36 CLOCKED FIRST-IN, FIRST-OUT MEMORY SGBS309A – AUGUST 1995 – REVISED APRIL 1998 D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Clocked FIFO Buffering Data From Port A to Port B Memory Size: 1024 × 36

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C − APRIL 1999 − REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D − Object Compatible With the TMS320C2xx Family − Source Code Compatible With

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SMJ320F240 DSP CONTROLLER SGUS029C - APRIL 1999 - REVISED SEPTEMBER 2004 D Processed to MIL-PRF-38535 QML D High-Performance Static CMOS Technology D Includes the T320C2xLP Core CPU D D D Dual 10-Bit Analog-to-Digital Conversion D - Object Compatible With the TMS320C2xx

Contextual Info: SN54ABT3614 64 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY WITH BUS MATCHING AND BYTE SWAPPING SGBS308F – AUGUST 1995 – REVISED MAY 2000 D D D D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 64 × 36 Clocked FIFOs

Contextual Info: SN54ACT3632 512 x 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SGBS310A – SEPTEMBER 1996 – REVISED APRIL 1998 D D D D D D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident Two Independent 512 × 36 Clocked FIFOs Buffering Data in Opposite Directions