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MC-4516DC72F-A10

Abstract: MC-4516DC72F-A12
Text: 18 ns 4.968 W CL = 3 100 MHz 10 ns 5.616 W 68.4 mW CL = 2 MC-4516DC72-A10B Active CL = 2 Z (MIN.) CL = 3 MC-4516DC72-A12 Burst cycle time (MAX.) MC-4516DC72-A10 , DC Characteristics (Recommended Operating Conditions unless otherwise noted) [ MC-4516DC72-A10 , one time during tCK(MIN.). 6 MC- 4516DC72 Z [ MC-4516DC72-A10B ] Parameter Symbol , tCL MC- 4516DC72 Synchronous Characteristics [ MC-4516DC72-A10 , 4516DC72 -A12 ] Parameter


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PDF MC-4516DC72 72-BIT MC-4516DC72 PD4564841 MC-4516DC72F-A10 MC-4516DC72F-A12
1998 - Not Available

Abstract: No abstract text available
Text: access time Family /CAS Latency Clock frequency (MAX.) MC-4516DC72-A10 CL = 3 CL = 2 MC-4516DC72-A12 CL , DATA SHEET MOS INTEGRATED CIRCUIT MC- 4516DC72 16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Description The MC- 4516DC72 is a 16,777,216 words by 72 bits synchronous , 1998 NS CP(K) Printed in Japan The mark · shows major revised points. © 1997 MC- 4516DC72 , : Gold plated [Double side] (400 mil TSOP (II) Package Mounted devices 2 MC- 4516DC72 Pin


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PDF MC-4516DC72 72-BIT MC-4516DC72 PD4564841 MC-4516DC72-A10 MC-4516DC72-A12
Not Available

Abstract: No abstract text available
Text: 12 ns 5.130 W CL = 2 MC-4516DC72-A12 Burst cycle time (MAX.) MC-4516DC72-A10 Clock , DATA SHEET MOS INTEGRATED CIRCUIT MC- 4516DC72 16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE REGISTERED TYPE Description The MC- 4516DC72 is a 16,777,216 words by 72 bits synchronous , i n t s © NEC Corporation 1997 NEC MC- 4516DC72 Ordering Information Part number , (II) (Socket Type) 2 Edge connector: Gold plated [Double side] MC- 4516DC72 NEC Pin


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PDF MC-4516DC72 72-BIT MC-4516DC72 uPD4564841 M200S-50A9
Not Available

Abstract: No abstract text available
Text: ns ms tR E F [ MC-4516DC72-A1 OB ] Param eter Symbol MIN. REF to REF/ACT command period ACT to , . [ MC-4516DC72-A1 OB] Speed version Clock cycle time [ns] Frequency [MHz] /CAS latency + 1 cycle [tR C , 30 ns 20 ns 30 ns 60 ns 15 NEC MC- 4516DC72 [ MC-4516DC72-A1 OB , -4516DC72F-A12 MC-4516DC72F- A1 OB Clock frequency 100 MHz 83 MHz 100 MHz Package MC- 4516DC72 Mounted devices , access time Family /CAS Latency Clock frequency (MAX.) MC-4516DC72-A10 CL = 3 CL = 2 MC-4516DC72-A12 CL


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PDF MC-4516DC72 72-BIT MC-4516DC72 uPD4564841 MC-4516DC72-A10 MC-4516DC72-A12 MC-4516DC72-A10B
Not Available

Abstract: No abstract text available
Text: MC-4516DC72-A1 OB (MIN.) CL = 3 MC-4516DC72-A12 Burst cycle time (MAX.) MC-4516DC72-A10 , delayed by one cycle. Therefore, DQ is delayed by one cycle. MC-4516DC72-A1 OB] Speed version -A10B , (Recommended Operating Conditions unless otherwise noted) MC-4516DC72-A10 , 4516DC72 -A12 ] Parameter Ic c i , ). tcK(MiN ). NEC MC- 4516DC72 MC-4516DC72-A10B ] Parameter Operating current Symbol , il (m ax .). NEC MC- 4516DC72 Synchronous Characteristics MC-4516DC72-A10 , 4516DC72


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PDF MC-4516DC72 72-BIT MC-4516DC72 uPD4564841 M200S-50A9
Not Available

Abstract: No abstract text available
Text: -4516D C72-A12 Burst cycle tim e (MAX.) MC-4516DC72-A10 Clock frequency 55 MHz 18 ns 4.968W , PRELIMINARY DATA SHEET_ NEC MOS INTEGRATED CIRCUIT MC- 4516DC72 16M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE BUFFERED TYPE Description The MC- 4516DC72 is a 16,777 , without notice. MC- 4516DC72 NEC Ordering Information C lock frequency Part num ber MHz (MAX , e c to r: Gold plated (400 mil TS O P (II) [Double side] MC- 4516DC72 NEC Pin


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PDF MC-4516DC72 16M-WORD 72-BIT MC-4516DC72 uPD4564841 200S-50A1
1997 - Not Available

Abstract: No abstract text available
Text: Family /CAS Latency Clock frequency (MAX.) MC-4516DC72-A10 CL = 3 CL = 2 MC-4516DC72-A12 CL = 3 CL = 2 , PRELIMINARY DATA SHEET MOS INTEGRATED CIRCUIT MC- 4516DC72 16 M-WORD BY 72-BIT SYNCHRONOUS DYNAMIC RAM MODULE BUFFERED TYPE Description The MC- 4516DC72 is a 16,777,216 words by 72 bits , The mark Z shows major revised points. ©NEC Corporation 1997 MC- 4516DC72 Ordering , pieces of 64M SDRAM : µPD4564841G5 (400 mil TSOP (II) [Double side] 2 MC- 4516DC72 Pin


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PDF MC-4516DC72 72-BIT MC-4516DC72 PD4564841 MC-4516DC72-A10 MC-4516DC72-A12
04564841G5

Abstract: NEC RF MODULE
Text: -BIT SYNCHRONOUS DYNAMIC RAM MODULE BUFFERED TYPE D escrip tion The MC- 4516DC72 is a 16,777,216 w ords by 72 , organization · C lock freq uency and Burst cycle tim e Family /CAS Latency Clock frequency (MAX.) MC- 4516DC72 * A10 CL = 3 CL = 2 MC- 4516DC72 -M2 CL = 3 CL = 2 100 MHz 67 MHz 83 MHz 55 MHz Burst cycle time (MIN.) 10 , tio n s (P relim inary) · All voltages are referenced to Vss (GND). MC- 4516DC72 · A fte r pow , }, MC- 4516DC72 M IN. MAX. 1,155 1,110 1,200 1,155 54 36 360 Unit mA Notes 1 mA 2 mA


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PDF MC-4516DC75 16M-WORD 72-BIT MC-4516DC72 uPD4564841 MC-4516DC72* MC-4516DC72-M2 04564841G5 NEC RF MODULE
Not Available

Abstract: No abstract text available
Text: 12 ns 7.560 W CL = 2 MC-4516DC72-A12 Burst cycle time (MAX.) MC-4516DC72-A10 Clock , D18, REGISTER, PLL CLOCK BUFFER A0 A1 A2 SA0 SA1 D1 - D18, REGISTER, PLL CLOCK BUFFER , n n a M 1 M2 (AREA A) J A1 (AREA A) ? ITEM M IL L IM E T E R S IN C H E S A 153.7 6.051 A1 1 5 3 .7 ± 0 .1 3 6 051 +0-006 b.U Sl _ 0 .0 0 5 0 .750


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PDF MC-4516DA72 72-BIT MC-4516DA72 uPD4564441 M200S-50A7
1998 - Not Available

Abstract: No abstract text available
Text: access time Family /CAS Latency Clock frequency (MAX.) MC-4516DC72-A10 CL = 3 CL = 2 MC-4516DC72-A12 CL , VSS /CAS NC VCC VSS /RAS VSS NC A11 VCC A0 A1 VSS DQ 35 DQ 34 VCCQ DQ 33 DQ 32 VSSQ DQ 27 DQ 26 VCCQ , 67 DQ 66 DQ 65 DQ 64 DQ 0 DQ 1 DQ 2 DQ 3 D18 SERIAL PD VCC SCL A0 A1 A2 SDA D1 - D18 , H K B I G C A1 (AREA A) D B S U1 U2 T M2 (AREA A) J (OPTIONAL HOLES) E ITEM A A1 B C D


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PDF MC-4516DA72 72-BIT MC-4516DA72 PD4564441 MC-4516DC72-A10 MC-4516DC72-A12
1998 - upd23c8000

Abstract: upd4502161 uPD23C8000X uPD4504161 *D431016 uPD23C16000
Text: frequency (MHz) 100 83 MC- 4516DC72 8M × 72 (ECC) MC-458DA72 2 1 100 83 100 83 Refresh cycle (cycles/ ms) 4K


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PDF -PC100 compliant64M compliant16M 168-pin 16-bit, upd23c8000 upd4502161 uPD23C8000X uPD4504161 *D431016 uPD23C16000
1997 - SO DIMM 72-pin

Abstract: "simm 72 pin" uPD27C8000 2620 dynamic ram simm 72 pin DIMM 72-pin SIMM 72 MC-422000F32 8k refresh simm 72 edo dram 72-pin SO DIMM
Text: -4516BA72 MC-4516DA72 MC-4516BC72 MC- 4516DC72 200-pin SDRAM DIMM 168-pin SDRAM DIMM 144-pin SDRAM SO


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PDF 8K/64* 4K/64 50-pin 32-pin PD4264405 PD4265405 SO DIMM 72-pin "simm 72 pin" uPD27C8000 2620 dynamic ram simm 72 pin DIMM 72-pin SIMM 72 MC-422000F32 8k refresh simm 72 edo dram 72-pin SO DIMM
2005 - 93lc46b1

Abstract: marking A5 sot-23 MARKING 3B1 SOT-23 3L7* MARKING 93Cxx MICROCHIP marking C.S l76a Marking A2 Microchip MARKING 93AA46B
Text: A1 FCLK Clock frequency - 3 2 1 MHz MHz MHz 4.5V VCC < 5.5V 2.5V VCC < 4.5V , (RDY/BSY) 9 Data In (16-BIT WORD ORGANIZATION) ERASE 1 11 A5 A4 A3 A2 A1 A0 , 9 READ 1 10 A5 A4 A3 A2 A1 A0 - D15-D0 25 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY) 25 WRAL 1 00 D15-D0 (RDY/BSY) 25 0 93XX46A OR 93XX46C , A1 A0 - (RDY/BSY) 10 x - (RDY/BSY) 10 x x - High-Z 10 x


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PDF 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C 93AA76A/B/C, 93lc46b1 marking A5 sot-23 MARKING 3B1 SOT-23 3L7* MARKING 93Cxx MICROCHIP marking C.S l76a Marking A2 Microchip MARKING 93AA46B
MC10137

Abstract: BIT 3195 G MC10141 MC10537 MCM10140 MCM10142 MCM10143 MCM10144 MCM10145 MCM10147
Text: SelB S1 A1 Cin cout -14 (2) -1 (5) "13 (1) Pq = 360 mW typ/pkg tpd (tvp) Cin to Cout = 2.2 ns , Load) tpd (typ): A1 to F - 6.5 n* Cn to Cn + 4 - 3.1 ns A1 to Pq » 5.0 n$ A1 to Gq = 4.5 ns A1 to Cn , Cn+4- 3.1 m Al to Pq = 5.0 ns A1 to Gq = 4.5 ns Al to Cn + 4 = 5.0 POSITIVE LOGIC NEGATIVE LOGIC , , A1 ,A2,A3 1.0 5.1 1.1 3.1 5.0 1.1 5.4 ns Rise Time, Fall Time t+,t- cn cn + 4 AO, A 1 ,A2,A3 1.0 3.2 , Propagation Delay t+, t+- A1 Fl - 2.6 10.4 3.0 6.5 10 3.0 10.8 ns t-+,t- - I I 2.6 10.4 3.0 6 5 10 3.0


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PDF MC10137 MC10537 64-Bit MCM10140 MC10141 MCM10142 MCM10143 256-Bit MCM10144 BIT 3195 G MCM10145 MCM10147
2007 - 93CXX

Abstract: l46A l46c l86a 93lc46b1 L56A L66C a86a L56C L86B
Text: VCC < 4.5V, CL = 100 pF 1.8V VCC < 2.5V, CL = 100 pF A1 FCLK A2 TCKH A3 , - (RDY/BSY) 9 93XX46B 93XX46C ORG = 1 16 ERASE 1 11 A5 A4 A3 A2 A1 A0 ERAL , 10 A5 A4 A3 A2 A1 A0 - D15-D0 25 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15-D0 (RDY , 01 WRAL 1 00 2-4 A6 A5 A4 A3 A2 A1 A0 - (RDY/BSY) 10 x - (RDY/BSY) 10 x x - 10 x x - 10 A6 A5 A4 A3 A2 A1 A0 - D7-D0


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PDF 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C 93AA76A/B/C, 93CXX l46A l46c l86a 93lc46b1 L56A L66C a86a L56C L86B
2005 - 93cxx

Abstract: L66C pic 93Cxx l46A TSSOP-6 a86a 93C46x l86a L46C A56A
Text: VCC < 4.5V, CL = 100 pF 1.8V VCC < 2.5V, CL = 100 pF A1 FCLK A2 TCKH A3 , - (RDY/BSY) 9 93XX46B 93XX46C ORG = 1 16 ERASE 1 11 A5 A4 A3 A2 A1 A0 ERAL , 10 A5 A4 A3 A2 A1 A0 - D15-D0 25 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15-D0 (RDY , 01 WRAL 1 00 2-4 A6 A5 A4 A3 A2 A1 A0 - (RDY/BSY) 10 x - (RDY/BSY) 10 x x - 10 x x - 10 A6 A5 A4 A3 A2 A1 A0 - D7-D0


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PDF 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C 93AA76A/B/C, 93cxx L66C pic 93Cxx l46A TSSOP-6 a86a 93C46x l86a L46C A56A
2005 - 93CXX

Abstract: l46a 93lc46b1 L46C l86a eeprom 93cxx C04-120 MC 342 transistor MC 139 transistor C66A
Text: - 3 2 1 MHz MHz MHz 4.5V VCC < 5.5V 2.5V VCC < 4.5V 1.8V VCC < 2.5V A1 FCLK , : 16 ) ERASE 1 11 - (RDY/BSY) 9 ERAL 1 00 A5 A4 A3 A2 A1 A0 1 0 x , 9 1 1 x x x x EWEN 1 00 READ 1 10 A5 A4 A3 A2 A1 A0 WRITE 1 01 A5 A4 A3 A2 A1 A0 D15-D0 (RDY/BSY) 25 WRAL 1 00 D15-D0 (RDY/BSY) 25 , x x - High-Z 10 A6 A5 A4 A3 A2 A1 A0 - D7-D0 18 A6 A5 A4 A3 A2 A1 A0


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PDF 93AA46A/B/C, 93LC46A/B/C, 93C46A/B/C 93AA56A/B/C, 93LC56A/B/C, 93C56A/B/C 93AA66A/B/C, 93LC66A/B/C, 93C66A/B/C 93AA76A/B/C, 93CXX l46a 93lc46b1 L46C l86a eeprom 93cxx C04-120 MC 342 transistor MC 139 transistor C66A
1999 - K30A transistor

Abstract: k30a transistor k30a MA1010 56301-to-56301 HTAP A10 ma1001 MA-1001 MD 1010 manual
Text: ; accessed with 31 wait states. ; Motorola Bootstrap Program A-1 ; The EPROM bootstrap code , ; bootstrap code starts at $ff0000 START clr a #$0a,X0 move #$3e,x1 movec omr, a1 and #$f,a move a1 , jclr #2,X:M_DSR,* movep X:M_DRXR,a2 asr #8,a,a _LOOP0 move a1 ,r0 move a1 ,r1 , high (i.e. data ready) Shift 8 bit data into A1 starting address for load save it in r1 a0 holds , movep X:M_DRXR,a2 asr #8,a,a ; ; ; ; ; ; ; _LBLB _LOOP2 movem a1 ,p:(r0)+ nop _LOOP1


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PDF DSP56301. DSP56301 DSP56301 24-bit K30A transistor k30a transistor k30a MA1010 56301-to-56301 HTAP A10 ma1001 MA-1001 MD 1010 manual
1995 - 16ROM

Abstract: skt 0110
Text: MOS MOS Integrated Circuit µPD17107( A1 ) PD17107 A1 ROM1 K512×16RAM16×I/O11 CPU17K 16 , -40110 RCCPD17107 A1 PD17107CX A1 -××× 16DIP300 mil PD17107GS A1 -××× 16SOP300 mil ×××ROM NEC IEI-620 PD17107A1 30 PD17103 A1 U10915JJ1V0DS00 November 1995 P © NEC Corporation 1995 µPD17107( A1 ) ROM 1 K 512×16 , mil 16SOP 300 mil PROM PD17P107 A1 TA = -4085 PROMROMROM


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PDF PD17107 16RAM16 I/O11 CPU17K I/O11N-ch 108-0171NEC 46017NEC 54024NEC 16ROM skt 0110
1990 - dsp56002 boot

Abstract: DSP56002 TRANSMITTER motorola mc
Text: 0100010101011101 10110111011010011010010101 1010100011010101 1001011001110100 01010 MOTOROLA A-1 SECTION CONTENTS A.1 A-2 INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . A-3 BOOTSTRAP AND ROM CODE MOTOROLA INTRODUCTION A.1 , listing is shown in Figure A-1 . MOTOROLA BOOTSTRAP AND ROM CODE A-3 INTRODUCTION , mem. ; and go get another 24-bit word. ; finish bootstrap Figure A-1 DSP56002 Bootstrap Program


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PDF 010010100bits 24-bit DSP56002 dsp56002 boot TRANSMITTER motorola mc
MC10137

Abstract: MC10141 MC10537 MCM10140 MCM10142 MCM10143 MCM10144 MCM10145 MCM10147 MCM10148
Text: SelB S1 A1 Cin cout -14 (2) -1 (5) "13 (1) Pq = 360 mW typ/pkg tpd (tvp) Cin to Cout = 2.2 ns , Load) tpd (typ): A1 to F - 6.5 n* Cn to Cn + 4 - 3.1 ns A1 to Pq » 5.0 n$ A1 to Gq = 4.5 ns A1 to Cn , - (15) 9- (.4) 22- (5) 23- SO S1 S2 S3 FO AO BO A1 B1 F 1 F 2 A2 B2 F 3 A3 °G B3 cn pG -2 , ): A1 to F =6.5 ns Cn to Cn+4 = 3.1 ns POSITIVE LOGIC A1 to Pq = 5.0 ns Al to Gq = 4.5 ns Al to Cn , Delay t+- t-+ S1 FI A1 , B1 2.7 10 2 3.0 6.6 10 2.6 10.2 ns Rise Time, Fall Time t+ t- S1 F 1 A1 , B 1


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PDF MC10137 MC10537 64-Bit MCM10140 MC10141 MCM10142 MCM10143 256-Bit MCM10144 MCM10145 MCM10147 MCM10148
1995 - uPD17107

Abstract: 0D19D M-0014 m11000
Text: MOS MOS Integrated Circuit µPD17107( A1 ) PD17107 A1 ROM1 K512×16RAM16×I/O11 CPU17K , HALTSTOP TA = -40110 RCCPD17107 A1 PD17107CX A1 -××× 16DIP300 mil PD17107GS A1 -××× 16SOP300 mil ×××ROM NEC IEI-620 PD17107A1 30 PD17103 A1 U10915JJ1V0DS00 November 1995 P © NEC Corporation 1995 µPD17107( A1 ) ROM 1 K 512×16 , mil 16SOP 300 mil PROM PD17P107 A1 TA = -4085 PROMROMROM


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PDF PD17107 16RAM16 I/O11 CPU17K I/O11N-ch RCCPD17107 PD17107CX 16DIP300 PD17107GS uPD17107 0D19D M-0014 m11000
2006 - NTP 7513

Abstract: tplink
Text: No file text available


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PDF SPRO-00516-04 FND1900ï FND1900A RV7-D040239-16 KSP71-0083-16-03 NTP 7513 tplink
2013 - f 1k MD 250v

Abstract: No abstract text available
Text: ±0.005 (V) ±0.01 (T) ±0.02 (Q) ±0.05 (A) ±0.1 (B) ±0.5 (D) ±1 (F) 5 to 30 ±0.1 (B) ±0.5 (D) ±1 (F) 0±5 (X) 0±2.5 (Y) 0±1 (Z)* 30 to 400k ±0.005 (V) ±0.01 (T) ±0.02 (Q) ±0.05 (A) ±0.1 (B) ±0.5 (D) ±1 (F) 0±5 (X) MD 5 to 30 ±0.1 (B) ±0.5 (D) ±1 (F) 0±5 (X) MB ±0.5 (D) ±1 (F) 0±5 (X) MA MC 1 to 5 5 to 30 ±0.1 (B) ±0.5 (D) ±1 (F) 0±5 (X) 0±2.5 (Y) 30 to 100 ±0.05 (A) ±0.1 (B) ±0.5 (D) ±1 (F) 100


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PDF MIL-PRF-55182/9. 29-Oct-2013 f 1k MD 250v
1995 - DSP56009

Abstract: No abstract text available
Text: 0100010101011101 10110111011010011010010101 1010100011010101 1001011001110100 01010 MOTOROLA A-1 SECTION CONTENTS Paragraph Number Section Page Number A.1 INTRODUCTION . . . . . . . . . , CONTENTS MOTOROLA INTRODUCTION A.1 INTRODUCTION This section presents the bootstrap , in Figure A-1 . MOTOROLA BOOTSTRAP ROM CONTENTS A-3 BOOTSTRAPPING THE DSP56009 A , =0, ; HRQE1-HRQE0=01, HIDLE=0, HBIE=0, HTIE=0, HRIE1-HRIE0=00 Figure A-1 DSP56009 Bootstrap Program (Sheet 1of 2


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PDF DSP56009 DSP56009
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