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DEM-PCM1800 Texas Instruments DEM-PCM1800: Instruction Manual for the PCM1800

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1999 - Not Available

Abstract: No abstract text available
Text: RC2 RC3 RD0 RD1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 36 35 34 33 32 31 30 29 , 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 (300 mil) RB7 RB6 RB5 RB4 RB3 RB2 RB1 RB0 , , the state machine will suspend the CPU awaiting a 16 -bit wide instruction to be shifted in. If the , 15 16 1 2 3 4 P9 P5 P3P4 P5 RB6 (Clock) RB7 (Data) 1 1 0 1 1 1 0 1 Execute FNOP Fetch 4-bit Instruction (TBLWT *) Reset 16 -bit Instruction Load or 16 -bit data Fetch or


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PDF PIC18CXXX PIC18C452 PIC18C252 PIC18C242 PIC18C442 PIC18C4XX PIC18CXXX PIC18CX DS39028A-page
1998 - m32r

Abstract: renesas M32R mitsubishi software manual Renesas spi sh LD24 mitsubishi 8-bit assembler language
Text: . 1-6 1.5 Program counter . 1-6 1.6 Data format , 1.4 1.5 1.6 1.7 CPU register General-purpose registers Control registers Accumulator Program , M32R CPU has 16 general-purpose registers, 5 control registers, an accumulator and a program counter , General-purpose registers The 16 general-purpose registers (R0 - R15) are of 32-bit width and are used to retain


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PDF pcdisp24 32-BIT m32r renesas M32R mitsubishi software manual Renesas spi sh LD24 mitsubishi 8-bit assembler language
1998 - M32R

Abstract: mitsubishi software manual LD24
Text: . 1-6 1.5 Program counter . 1-6 1.6 Data format , 1.4 1.5 1.6 1.7 CPU register General-purpose registers Control registers Accumulator Program , M32R CPU has 16 general-purpose registers, 5 control registers, an accumulator and a program counter , General-purpose registers The 16 general-purpose registers (R0 - R15) are of 32-bit width and are used to retain


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PDF 32-BIT J24532 M32R mitsubishi software manual LD24
2010 - transistor DATA REFERENCE handbook

Abstract: NII51017-10 IMMED26 "Overflow detection" RC3130
Text: words contain: A 6-bit opcode field OP Two 5-bit register fields A and B A 16 , : 31 30 29 28 27 26 25 A 24 23 22 21 20 19 18 17 16 , 28 27 26 25 A 24 23 22 21 20 B 19 18 17 16 15 14 , 16 15 14 13 12 11 10 9 8 7 6 IMMED26 5 4 3 2 1 0 , macros. These macros return 16 -bit signed values or 16 -bit unsigned values depending on where they are


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PDF NII51017-10 transistor DATA REFERENCE handbook IMMED26 "Overflow detection" RC3130
2003 - SKPT

Abstract: No abstract text available
Text: Nios Embedded Processor 16 -Bit Programmer's Reference Manual 101 Innovation Drive San Jose, CA , Date: January 2003 Copyright Nios Embedded Processor 16 -Bit Programmer's Reference Manual , provides comprehensive information about the Altera® Nios® 16 -bit CPU. The terms Nios processor or Nios , Altera Nios Embedded Processor 16 -Bit Programmer's Reference Manual For the most up-to-date , office or sales representative. Altera Corporation Nios Embedded Processor 16 -Bit Programmer


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PDF 16-Bit MNL-NIOS16PROG-3 SKPT
2000 - PIC18CXXX

Abstract: No abstract text available
Text: * RC2/CCP1 RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 40 39 38 37 , awaiting a 16 -bit wide instruction to be shifted in. If the instruction is a TBLWT, the state machine , 15 16 1 2 3 4 RB6 (Clock) P5 P3P4 P5 RB7 (Data) 0 1 0 0 0 1 0 0 Execute FNOP Fetch 4-bit Instruction Reset 16 -bit Instruction Load or 16 -bit data Fetch or Perform , PIC18CXXX 2.2.3 NOP SERIAL INSTRUCTION EXECUTION 2.2.4 ONE CYCLE 16 -BIT INSTRUCTIONS The NOP serial


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PDF PIC18CXXX PIC18CXXX PIC18C452 PIC18C252 PIC18C242 PIC18C442 DS39028B-page
2002 - IFRZ 34

Abstract: PFX 1000 ifrz54
Text: Nios Embedded Processor 16 -Bit Programmer's Reference Manual 101 Innovation Drive San Jose, CA , : 2.1 04/02 Copyright Nios 16 -Bit Programmer's Reference Manual Copyright © 2002 Altera , provides comprehensive information about the Altera® Nios® 16 -Bit CPU. The terms Nios processor or Nios , Nios 16 -Bit Programmer's Reference Manual For the most up-to-date information about Altera products , representative. Altera Corporation About this Manual Typographic Conventions Nios 16 -Bit Programmer


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PDF 16-Bit MNL-NIOS16PROG-2 IFRZ 34 PFX 1000 ifrz54
stk 490 110

Abstract: R7EH uPD77112 uPD77111 uPD77110 uPD77019 uPD77018A uPD77018 stk 490 140 uPD77016
Text: . 16 1.2.1 General-purpose register partition format , . 16 1.2.2 Data pointer modification , . 16 1-2 Formats of Instruction Words , ##, DPn%%, !DPn## (n = 4 to 7) dp_imm DPn##imm (n = 0 to 7) * xxx 16 R0 to R7 Memory , . Figure 1-1. Partition Formats of General-Purpose Registers 39 0 R0 to R7 D 39 16 15


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PDF PD77016 PD77015 PD77016 PD77017 PD77018 PD77018A PD77019 PD77110 PD77111 PD77112 stk 490 110 R7EH uPD77112 uPD77111 uPD77110 uPD77019 uPD77018A uPD77018 stk 490 140 uPD77016
1997 - M32R

Abstract: LD24
Text: . 1-6 1.5 Program counter . 1-6 1.6 Data format , 1.4 1.5 1.6 1.7 CPU register General-purpose registers Control registers Accumulator Program , M32R CPU has 16 general-purpose registers, 5 control registers, an accumulator and a program counter , General-purpose registers The 16 general-purpose registers (R0 - R15) are of 32-bit width and are used to retain


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PDF 32-BIT J24532 M32R LD24
1998 - mitsubishi 8-bit assembler language

Abstract: No abstract text available
Text: . 1-6 1.5 Program counter . 1-6 1.6 Data format , 1.4 1.5 1.6 1.7 CPU register General-purpose registers Control registers Accumulator Program , M32R CPU has 16 general-purpose registers, 5 control registers, an accumulator and a program counter , General-purpose registers The 16 general-purpose registers (R0 - R15) are of 32-bit width and are used to retain


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PDF pcdisp24 32-BIT mitsubishi 8-bit assembler language
2002 - mitsubishi 8-bit assembler language

Abstract: No abstract text available
Text: MITSUBISHI 16 -BIT SINGLE-CHIP MICROCOMPUTER M16C FAMILY M16C/60 M16C/20 Series Software Manual , . 8 1.6 Internal State after Reset is Cleared , of cycles #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An] dsp:8[SB/FB , of cycles #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An] dsp:8[SB/FB , instruction code /number of cycles #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An


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PDF M16C/60, M16C/20 mitsubishi 8-bit assembler language
2000 - PIC18C4X2

Abstract: PIC18CXXX family 18CXXX ds39026 18CXX PIC18CXXX PIC18C858 PIC18C452 PIC18C252 PIC18CXX8
Text: 16 17 18 19 20 MCLR/VPP RA0/AN0 RA1/AN1 RA2/AN2/VREFRA3/AN3/VREF+ RA4/T0CKI RA5/AN4/SS , 15 16 17 PIC18C4X2 28 27 26 25 24 23 22 21 20 19 18 RA4/T0CKI RA5/AN4/SS/LVDIN , 17 16 15 14 13 12 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS VDD RB0/INT0 RB1 , RC3/SCK/SCL RD0/PSP0 RD1/PSP1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 , 23 22 21 20 19 18 17 16 15 RB7 RB6 RB5 RB4 RB3/CCP2* RB2/INT2 RB1/INT1 RB0/INT0


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PDF PIC18CXXX PIC18CXXX PIC18C242 PIC18C858 PIC18C442 PIC18CXX2 PIC18CXX8 PIC18C658 PIC18C252 PIC18C958 PIC18C4X2 PIC18CXXX family 18CXXX ds39026 18CXX PIC18C858 PIC18C452 PIC18C252 PIC18CXX8
DSP56K

Abstract: A-18
Text: is faster and simpler to use the DSP56K simulator to calculate instruction timing.) Example 16 , , assuming that the 16 -bit bus control register contains the value $1135, external X memory accesses require , , assuming that the 16 -bit bus control register contains the value $2246, external P memory accesses require , programmed into the DSP56K bus control register (BCR). Thus, assuming that the 16 -bit bus control register , circuits. Note 2: The WAIT instruction takes a minimum of 16 cycles to execute when an internal interrupt


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PDF DSP56K DSP56K A-18
1995 - H8/520

Abstract: 004B 004C 00FF CPU H8 534
Text: Hitachi-original microcontrollers is built around a 16 -bit CPU core that offers enhanced speed and a large address , in application-specific integrated circuits. Its Hitachi-original architecture features eight 16 -bit general registers, internal 16 -bit data paths, and an optimized instruction set. Section 1 summarizes , listed below. · · · · · * General-register machine - Eight 16 -bit general registers - Seven control registers (two 16 -bit registers, five 8-bit registers) High speed: maximum 10MHz At


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PDF H8/500 ADE-602-021 16-bit H8/500 H8/520/532/534/536) H8/510/570) H8/520 004B 004C 00FF CPU H8 534
2001 - DS30475

Abstract: 18CXX 18C601 18CXXX PIC18CXXX PIC18CXX ds39026 PIC18C858 PIC18C601 PIC18C452
Text: minimum resolution of 0.25V. 1.2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 , FIGURE 1-2: 6 5 4 3 2 1 44 43 42 41 40 PLCC 7 8 9 10 11 12 13 14 15 16 171 , 22 21 20 19 18 17 16 15 14 13 12 RC7/RX/DT RD4/PSP4 RD5/PSP5 RD6/PSP6 RD7/PSP7 VSS , 13 14 PIC18C2X2 DIP, SOIC, Windowed CERDIP 28 27 26 25 24 23 22 21 20 19 18 17 16 , RF2/AN7/C1OUT 16 33 RC2/CCP1 PIC18C658 8 RC0/T1OSO/T13CKI RC6/TX/CK RC7/RX/DT


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PDF PIC18CXXX PIC18CXXX PIC18C242 PIC18C801 PIC18C442 PIC18C658 PIC18C452 PIC18CXX2 PIC18CXX8 PIC18C601/801 DS30475 18CXX 18C601 18CXXX PIC18CXX ds39026 PIC18C858 PIC18C601 PIC18C452
1997 - V810

Abstract: V850 instruction set V850 code generation "saturation processing" v850family V853 V852 V851 V830 V800
Text: V850 FAMILY TM 32-/ 16 -BIT SINGLE-CHIP MICROCONTROLLER ARCHITECTURE V851 TM V852 TM V853 TM , systems employed 8-bit or 16 -bit microcontrollers so far. However,the performance level of these , Hardware interlock on register/flag hazards · Memory space Program space : 16 MB linear Data space , instructions · On-chip multiplier executing multiplication in 1 to 2 clocks ( 16 bits ¥ 16 bits Æ 32 bits) 2 , queue PC ROM/ PROM Internal peripheral I/O 32-bit barrel shifter Multiplier 16 × 16 32


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PDF 32-/16-BIT U10243EJ4V0UM00 V810 V850 instruction set V850 code generation "saturation processing" v850family V853 V852 V851 V830 V800
2013 - IVOR33

Abstract: No abstract text available
Text: Freescale Semiconductor Application Note Document Number: AN4648 Rev. 1, 3/2013 VLE 16 , .2 4 Book E or VLE instruction decoding.2 5 Decoding 16 -bit or 32 , use both variable length encoding (VLE) 16 -bit and 32-bit instructions and Book E 32-bit instructions , -bit instructions; an increment of 2 bytes is required for VLE 16 -bit instructions. 4 Book E or VLE instruction , . There are several ways to determine whether a Book E or a VLE instruction was used. VLE 16 -bit and 32


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PDF AN4648 16-bit 32-bit MPC56xx IVOR33
1997 - 8086 opcode list

Abstract: invalid opcode RISC86 AMD-K6 Processor basic operation
Text: used for pixel information and 16 -bit data is used for audio samples. The new MMX registers allow data , ) Unsigned integer range(0 to 28­1) Packed word Four 16 -bit words packed into 64-bits Signed integer , bits x 8) Packed bytes 63 56 55 B7 40 39 48 47 B6 B5 32 31 B4 24 23 16 15 B2 B3 0 87 B1 B0 ( 16 bits x 4) Packed words 63 32 31 48 47 W3 W2 0 16 15 , fault (14) Floating-point exception pending ( 16 ) Alignment check (17) X One of the instruction


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PDF mmreg2/mem64 64-bit 8086 opcode list invalid opcode RISC86 AMD-K6 Processor basic operation
2005 - ADSP-21990

Abstract: ADSP-21991 ADSP-21992 PF10
Text: ) Register . 1-6 Interrupt Mask (IMASK) Register and Interrupt , Load . 6-27 Indirect 16 -Bit Memory Read/Write-Postmodify . 6-30 Indirect 16 -Bit Memory Read/Write-Premodify , /Write-Immediate Premodify . 6-54 Indirect 16 -Bit Memory Write-Immediate Data , 8-33 Type 16 : Shift Reg0 . 8-34


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PDF ADSP-219x ADSP-219x/2191 ADSP-21990 ADSP-21991 ADSP-21992 PF10
NII51017-7

Abstract: mulxss "Overflow detection"
Text: contain: A 6-bit opcode field OP Two 5-bit register fields A and B A 16 bit immediate data , 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 A Altera , 22 A 21 B 8­2 Nios II Processor Reference Handbook 20 19 18 17 16 15 14 13 12 11 10 , 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 IMMED26 Altera Corporation May 2007 9 , available macros. These macros return 16 -bit signed values or 16 -bit unsigned values depending on where


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PDF NII51017-7 mulxss "Overflow detection"
2003 - FFE0016

Abstract: nec dsp 32bit opcode FC151
Text: . User's Manual 16 M16C/60, M16C/20, M16C/Tiny Series Software Manual RENESAS 16 -BIT SINGLE-CHIP , . 8 1.6 Internal State after Reset is Cleared , . 16 1.8.1 Data Arrangement in Register . 16 1.8.2 Data Arrangement in Memory , #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An] dsp:8[SB/FB] [An] An


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PDF M16C/60, M16C/20, M16C/Tiny M16C-85-0204 16-BIT FFE0016 nec dsp 32bit opcode FC151
2001 - FC06F

Abstract: No abstract text available
Text: ADVANCED AND EVER ADVANCING MITSUBISHI ELECTRIC MITSUBISHI 16 -BIT SINGLE-CHIP MICROCOMPUTER , . 8 1.6 Internal State after Reset is Cleared , of cycles #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An] dsp:8[SB/FB , of cycles #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An] dsp:8[SB/FB , instruction code /number of cycles #IMM #IMM20 #IMM16 #IMM8 abs16 dsp: 16 [SB] dsp: 16 [An


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PDF 16-BIT M16C/60 M16C/20 M16C/60, M16C/20 M16C/60 FC06F
R7EH

Abstract: uPD77017 uPD77113 uPD77112 uPD77111 uPD77110 uPD77019 uPD77018A uPD77018 uPD77016
Text: . 16 1.2.1 General-purpose register partition format , . 16 1.2.2 Data pointer modification , . 16 1-2 Formats of Instruction Words , ##, DPn%%, !DPn## (n = 4 to 7) dp_imm DPn##imm (n = 0 to 7) * xxx 16 R0 to R7 Memory , . Figure 1-1. Partition Formats of General-Purpose Registers 39 0 R0 to R7 D 39 16 15


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PDF d88-6130 R7EH uPD77017 uPD77113 uPD77112 uPD77111 uPD77110 uPD77019 uPD77018A uPD77018 uPD77016
MIPS R3000A

Abstract: R3000A 1000H MIPS16 TX39 TX39 Family Hardware
Text: performance of a 16 -bit architecture. The instruction set of the TX19 includes as a subset the 32 , standard ASSP products. 16 -Bit and 32-Bit ISA Modes · The 16 -bit instructions are object-code , . · · · · Efficient run-time switching between 16 -bit and 32-bit ISA modes through an , /X and the 900/L1, 8-bit and 16 -bit CISC processors from Toshiba. The TX19 has two ISA modes, 16 -bit and 32-bit. It provides for efficient run-time switching between 16 -bit and 32-bit ISA modes through


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PDF 900/L1 32-bit 16-bit 32-bit R3000A MIPS R3000A 1000H MIPS16 TX39 TX39 Family Hardware
2002 - R3000A

Abstract: MIPS R3000A dynamic LED traffic light signs details R3000a Performance Semiconductor YG6260 TX39 MIPS16 IEC825-1 1000H RFT Semiconductors
Text: 32bit instruction set architecture (ISA) implemented by the TX19. · Chapter 4, " 16 -Bit ISA Summary , Preface · Appendix B, " 16 -Bit ISA Details," gives a complete description of each instruction available in 16 -bit ISA mode. · Appendix C, "Programming Restrictions," summarizes the restrictions , .1-4 1.3.2 Instruction Format. 1-6 1.3.3 Instruction Pipelines. 1-6


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PDF 32-Bit MIPS16, R3000A MIPS R3000A dynamic LED traffic light signs details R3000a Performance Semiconductor YG6260 TX39 MIPS16 IEC825-1 1000H RFT Semiconductors
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