HD74HC11 Search Results

Contextual Info: HD74HC113 Dual J-K Flip-Flops with Preset REJ03D0563-0200 (Previous ADE-205-436) Rev.2.00 Oct 11, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is independent of the clock and

Contextual Info: HD74HC114 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock T h u flip-flop it edge sensitive to the clock input and change PIN ARRANGMENT state on the negative transition of the dock pulse. Each flipflop hai independant J, K, and preset inputs and Q and Q

74HC114

Contextual Info: HD74HC114 D u al J-K F lip -F lo p s with Preset, Common Clear, and Common Clock This flip-flop is edge sensitive to the clock input and change PIN ARRANGMENT state on the negative transition of the clock pulse. Each flipflop has independent J, K, and preset inputs and Q and Q

Contextual Info: HD74HC112 Each flip -flo p has independent J . K, # Dual J-K Flip-Flops with P reset and C le a r preset, clear, and clock inputs and Q and Q outputs. This device is edge | PIN ARRANGEMENT sensitive to the d o c k in put and change state on the negative going transi­

Contextual Info: HITACHI/ LOGIC/ARRAYS/NEM *Ì2~ " ¿ E l 4 4 ^ 3 0 3 □ □ l G 3 b [ì S 92D HD74HC112 # Dual J-K Flip-Flops Each flip -flo p has independent J, K , preset, clear, and clock 10369 T - % - D “7-07 w ith P re s e t and C le a r | PIN ARRANGEMENT inputs and Q and Q outputs. This device is edge sensitive to

Hitachi DSA00279

Contextual Info: HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

Hitachi DSA00279

Contextual Info: HD74HC113 Dual J-K Flip-Flops with Preset Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is

Contextual Info: HD74HC113 # Dual J-K Flip-Flops i-vith Preset • PIN ARRANGMENT This flip-flop ii edge sensitive to the dock input and change state on the negative going transition of the dock pulse. Each \~ J~ ~ one has independent v, K, dock, and preset inputs and Q -«nd

HD74HC11FPEL

Abstract: HD74HC11 sem 2005 SOP14 package HD74HC11P HD74HC11RPEL PRDP0014AB-B PRSP0014DF-B
Contextual Info: HD74HC11 Triple 3-input AND Gates REJ03D0539-0200 Previous ADE-205-411 Rev.2.00 Oct 06, 2005 Features • • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V

Contextual Info: HITACHI/ LOGIC/ARRAYS/MEd ^5 T>Ë| i t i n t 2 0 3 0Q10330 Q 92D HD74HC11 # 103 30 D TVV 3 ' 2 / Triple 3-input AND Gates • F E A T UR E S I PIN ARRANGEMENT • High Speed Operation: tpcj= 9ns typ. C/_=50pF • High O u tptt Current: Fanout of 10 LSTTL Loads

Contextual Info: HITACHI/ LOGIC/AR RAYS/MEM =IS DË1 4 ln t a 0 3 0010371 3 | 92D HD74HC113 10371 D T -q o -O”7 -07 Dual J-K Flip-Flops (with Preset This flip-flop is edge sensitive to the clock input end change | PIN ARRANGMENT state on the negative going transition of the clock pulse. Each

HD74HC11

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN 2054.11
Contextual Info: HD74HC11 Triple 3-input AND Gates ADE-205-411 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 9 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Contextual Info: HD74HC112 • Dual J K Flip-Flops with P reset and Clear Each flip-flop has independent J, K, preset, clear, and clock • PIN ARRANGEMENT input» and Q and Q outputs. This device is edge sensitive to the d o c k input and change state on the negative going transi­

Contextual Info: HD74HC112 Each flip -flo p has independent J, K, # Dual J-K Flip-Flops w ith P re s e t and C le a r preset, clear, and clock | PIN ARRANGEMENT inputs and Q and Q outputs. This device is edge sensitive to the clock in put and change state on the negative going transi­

HD74HC112

Abstract: PRSP0016DH-B HD74HC112FPEL HD74HC112P PRDP0016AE-B
Contextual Info: HD74HC112 Dual J-K Flip-Flops with Preset and Clear REJ03D0562-0200 (Previous ADE-205-435) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear and preset are independent of

Hitachi DSA00279

Contextual Info: HD74HC114 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops

Hitachi DSA00279

Contextual Info: HD74HC112 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse.

FP-14DN

Abstract: HD74HC113 DP-14 FP-14DA Hitachi DSA003765
Contextual Info: HD74HC113 Dual J-K Flip-Flops with Preset Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and preset inputs and Q and Q inputs. Preset is

HD74HC112

Abstract: Hitachi DSA003739
Contextual Info: HD74HC112 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Clear

Contextual Info: HD74HC11 # Triple 3-input AND Gates • FEATURES I PIN ARRANGEMENT • High Speed Operation: tpcj = 9ns ty p . C/_ = 5 0 p F • High O u tp u t C urrent: Fanout o f 10 L S T T L Loads • Wide Operating Voltage: Vcc = 2 ~ 6 V • Low In p u t C urrent: 1/uA max.

DP-14

Abstract: FP-14DA FP-14DN HD74HC11 Hitachi DSA00333
Contextual Info: HD74HC11 Triple 3-input AND Gates Features • • • • • High Speed Operation: tpd = 9 ns typ CL = 50 pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 1 µA max (Ta = 25°C)

DP-14

Abstract: FP-14DA FP-14DN HD74HC114 Hitachi DSA00334
Contextual Info: HD74HC114 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops are

HC125

Abstract: HC126 HD74HC128 HC-126 HD74HC1125 HD74HC126
Contextual Info: HD74HC1125, HD74HC12 6 * S Ä Ä * The HD74HC125, HD74HC128 faquir* the 3-«ta«e control input C to be taken high to put the output into the high Im­ pedance condition, whereat the HD74HC125, HD74HC126 requires the control input to be low to put the output into

Contextual Info: HD74HC11 # Triple 3 -input AND Gates PIN ARRANGEMENT • FEATURES • • • • • High Speed Operation: tpdm9ns typ. C/_ *50pF High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: Vcc = 2 ~ 6 V Low Input Current: 1/uA max. Low Quiescent Supply Current:/cc (static) = 1>iA max. (7a> 25°C)