HD74HC10 Search Results

Contextual Info: Ì5 HITACHI/ LOGIC/ARRAYS/MEM DE] 4 4 ^ 5 0 3 0GlD3b3 92D HD74HC107 4 |~ V T ~ lf b ~ '0 7 - '0 7 10363 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse.

HD74HC107

Abstract: Hitachi DSA00279
Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is

R16-14

Contextual Info: HD74HC107 # Dual J-K Flip-Flops with Clear This flip -flo p is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and

Contextual Info: HD74HC108 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each PIN ARRANGMENT flip-flop has independent J, K, and preset inputs and Q and

HD74HC107

Abstract: HD74HC107P HD74HC107FPEL PRDP0014AB-B PRSP0014DF-B
Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear REJ03D0559-0200 (Previous ADE-205-432) Rev.2.00 Oct 06, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and

74hc108

Contextual Info: HD74HC108 # Dual J-K Flip-Flops with Preset, Common Clear, and Common Clock This flip -flo p is edge sensitive to the clock in put and change PIN ARRANGMENT state on the negative transition of the clock pulse. Each flip -flo p has independent J, K , and preset inputs and Q and

Contextual Info: HD74HC108 Dual J-K Flip-Flops w ith Preset, Com m on C lear, a n d Common C lock # This flip-flop it edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop h a t independent J, K, and preset input« and Q and

Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the clock input and change | PIN ARRANGEMENT state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is independent of the clock and

DP-14

Abstract: FP-14DA FP-14DN HD74HC108 TTP-14D Hitachi DSA00395
Contextual Info: HD74HC108 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each flip-flop has independent J, K, and preset inputs and Q and Q outputs. Two flip-flops are

HD74HC109

Abstract: Hitachi DSA00396
Contextual Info: HD74HC109 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear

506 K 7 20 7

Abstract: HD74HC109 Hitachi DSA00221
Contextual Info: HD74HC109 Dual J-K Flip-Flops with Preset and Clear ADE-205-434 (Z) 1st. Edition Sep. 2000 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear

Contextual Info: HITACHI/ LOGIC/ARRAYS/flEM ~T5 D Ë J 441t,5G3 GDlGBb? 1 | ~ 92 D HD74HC109 # 10367 Dual J-K Flip-Flops with Preset and Clear Each flip-flop has independent J, K, preset, clear and clock | PIN ARRA N G EM EN T inputs and Q and Q outputs. This device is edge sensitive to

Hitachi DSA00279

Contextual Info: HD74HC109 Dual J-K Flip-Flops with Preset and Clear Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse.

HD74HC10

Abstract: Hitachi DSA0095 DP-14 FP-14DA FP-14DN TTP-14D
Contextual Info: HD74HC10 Triple 3-input NAND Gates ADE-205-410 Z 1st. Edition Sep. 2000 Features • • • • • High Speed Operation: tpd = 10.5 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max

Contextual Info: HD74HC109 # Oual J-R Fhp-Flops with Preset and Clear Each flip-flop ha* in d e p e n d e n t j , K, preset, clear and clock Input* and Q and Q outputs. This device it edge sensitive to the dock input and change« «ate on the positive going transition of the dock pulse. Clear and preset are indepen­

DP-14

Abstract: FP-14DA FP-14DN HD74HC107 TTP-14D Hitachi DSA00395
Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is

Contextual Info: HD74HC10 • Triple 3-input NAND Gates • FEATURES I PIN ARRANGEMENT • High Speed Operation: \p d = 10.5ns typ. Q _=50pF • High Output Current: Fanout of 10 LSTTL Loads • Wide Operating Voltage: Vcc = 2 ~ 6V • Low Input Current: 1jjA max. • Low Quiescent Supply Current:/cc (static) = 1;uA max. (Ta = 25°C)

Contextual Info: HD74HC109 « d»* J-K Flip-Flops with Preset and Clear Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the dock input and changes state on the positive going transition of the d ock pulse. Clear and preset are indepen­

HD74HC109

Abstract: HD74HC109FPEL HD74HC109P HD74HC109RPEL PRDP0016AE-B PRSP0016DH-B
Contextual Info: HD74HC109 Dual J-K Flip-Flops with Preset and Clear REJ03D0561-0200 (Previous ADE-205-434) Rev.2.00 Oct 11, 2005 Description Each flip-flop has independent J, K, preset, clear and clock inputs and Q and Q outputs. This device is edge sensitive to the clock input and changes state on the positive going transition of the clock pulse. Clear and preset are independent of

HD74HC108

Abstract: PRSP0014DE-A
Contextual Info: HD74HC108 Dual J-K Flip-Flops with Preset, Common Clear and Common Clock REJ03D0560-0200 (Previous ADE-205-433) Rev.2.00 Oct 11, 2005 Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. Each

HD74HC107

Abstract: DP-14 FP-14DA FP-14DN Hitachi DSA00221
Contextual Info: HD74HC107 Dual J-K Flip-Flops with Clear ADE-205-432 (Z) 1st. Edition Sep. 2000 Description This flip-flop is edge sensitive to the clock input and change state on the negative going transition of the clock pulse. Each one has independent J, K, clock, and clear inputs and Q and Q outputs. Clear is

Contextual Info: H ITA C H I/ LOGIC/ARRAYS/MEN TE D Ë | 44i h a D 3 DülDBbS 92D HD74HC108 10365 fl D Dual J-K Flip-Flops with Preset Common Clear, and Common Clock PIN ARRANGMENT T h is flip -flo p is edge sensitive to the clo c k in p u t and change state o n the negative tran sition o f the clo c k pulse. Each

Contextual Info: HD74HC10 • Triple 3-input HAND Gates • FEATURES • • • • • | PIN ARRANGEMENT High Speed Operation: tprf-IO.&n* typ. C^ -50pF High Output Currant: Fanout of 10 LSTTL Load* Wide Operating Voltage l/cc-2~6V Low Input Currant: 1j»A max. Low Quiescent Supply Currant: Icc (static) - 1/iA max. (r»«2B°CI

Contextual Info: HD74HC107 • Dual J-K Flip-Flops with Clear This flip-flop is edge sensitive to the dock Input and change state on the negative going transition of the clock pulse. Each one hat independent J, K, dock, and dear inputs and Q and Q outputs. Clear It independent of the clock and