CY7C1312CV18 Search Results
CY7C1312CV18 Datasheets (12)
| Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
|---|---|---|---|---|---|---|---|
| CY7C1312CV18 |   | 18-Mbit QDR-II SRAM 2-Word Burst Architecture | Original | 1.1MB | 26 | ||
| CY7C1312CV18-167BZC |   | 18-Mbit QDR -II SRAM 2-Word Burst Architecture | Original | 922.03KB | 24 | ||
| CY7C1312CV18-167BZC |   | Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA | Original | 25 | |||
| CY7C1312CV18-167BZI |   | 18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V | Original | 922.03KB | 24 | ||
| CY7C1312CV18-167BZI |   | Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 167MHZ 165FBGA | Original | 25 | |||
| CY7C1312CV18-200BZC |   | 18-Mbit QDR -II SRAM 2-Word Burst Architecture | Original | 922.03KB | 24 | ||
| CY7C1312CV18-200BZC |   | Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 200MHZ 165FBGA | Original | 25 | |||
| CY7C1312CV18-250BZC |   | 18-Mbit QDR -II SRAM 2-Word Burst Architecture | Original | 922.03KB | 24 | ||
| CY7C1312CV18-250BZC |   | Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA | Original | 25 | |||
| CY7C1312CV18-250BZI |   | Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA | Original | 25 | |||
| CY7C1312CV18-250BZXC |   | 18-Mbit QDR -II SRAM 2-Word Burst Architecture; Architecture: QDR-II, 2 Word Burst; Density: 18 Mb; Organization: 1Mb x 18; Vcc (V): 1.7 to 1.9 V | Original | 922.03KB | 24 | ||
| CY7C1312CV18-250BZXC |   | Memory, Integrated Circuits (ICs), IC SRAM 18MBIT 250MHZ 165FBGA | Original | 25 | 
CY7C1312CV18 Price and Stock
| Infineon Technologies AG CY7C1312CV18-250BZCIC SRAM 18MBIT PAR 165FBGA | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | CY7C1312CV18-250BZC | Tray | 136 | 
 | Buy Now | ||||||
| Infineon Technologies AG CY7C1312CV18-250BZIIC SRAM 18MBIT PAR 165FBGA | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | CY7C1312CV18-250BZI | Tray | 
 | Buy Now | |||||||
| Infineon Technologies AG CY7C1312CV18-167BZCIC SRAM 18MBIT PAR 165FBGA | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | CY7C1312CV18-167BZC | Tray | 136 | 
 | Buy Now | ||||||
| Infineon Technologies AG CY7C1312CV18-200BZCIC SRAM 18MBIT PARALLEL 165FBGA | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | CY7C1312CV18-200BZC | Tray | 136 | 
 | Buy Now | ||||||
| Infineon Technologies AG CY7C1312CV18-167BZIIC SRAM 18MBIT PAR 165FBGA | |||||||||||
| Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
|   | CY7C1312CV18-167BZI | Tray | 
 | Buy Now | |||||||
CY7C1312CV18 Datasheets Context Search
| Catalog Datasheet | Type | Document Tags | |
|---|---|---|---|
| Contextual Info: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR-II SRAM 2-Word Burst Architecture Features Functional Description • Separate Independent Read and Write data ports — Supports concurrent transactions • 250-MHz clock for high bandwidth | Original | CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit 250-MHz | |
| CY7C1314CV18
Abstract: CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC 
 | Original | CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1310CV18 CY7C1312CV18 CY7C1910CV18 CY7C1314CV18-250BZXC | |
| CY7C1310CV18
Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18 
 | Original | CY7C1310CV18, CY7C1910CV18 CY7C1312CV18, CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1312CV18 CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1910CV18 | |
| CY7C1312CV18
Abstract: CY7C1314CV18 
 | Original | CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18 CY7C1314CV18 | |
| Contextual Info: CY7C1312CV18 CY7C1314CV18 18-Mbit QDR II SRAM 2-Word Burst Architecture 18-Mbit QDR® II SRAM 2-Word Burst Architecture Features Configurations • Separate independent Read and Write Data Ports ❐ Supports concurrent transactions CY7C1312CV18 – 1M x 18 | Original | CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18 | |
| Contextual Info: CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 PRELIMINARY 18-Mbit QDR -II SRAM 2 Word Burst Architecture Features Configurations Separate Independent read and write data ports ❐ Supports concurrent transactions • 250 MHz clock for high bandwidth | Original | CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1310CV18, | |
| CY7C1312CV18
Abstract: CY7C1314CV18 
 | Original | CY7C1312CV18 CY7C1314CV18 18-Mbit CY7C1312CV18 CY7C1314CV18 | |
| CY7C1310CV18
Abstract: CY7C1312CV18 CY7C1314CV18 CY7C1910CV18 
 | Original | CY7C1310CV18 CY7C1910CV18 CY7C1312CV18 CY7C1314CV18 18-Mbit 250-MHz RC1910CV18 18/CY7C1910CV18/CY7C1312CV18/CY7C1314CV18 CY7C1310CV18 CY7C1312CV18 CY7C1314CV18 CY7C1910CV18 |