CY7C1303CV25 Search Results

Contextual Info: CY7C1303CV25 CY7C1306CV25 PRELIMINARY 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description • Separate independent read and write data ports ❐ Supports concurrent transactions ■ 167 MHz clock for high bandwidth ❐ 2.5 ns Clock-to-Valid access time

Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-44701 Spec Title: CY7C1306CV25, 18-MBIT BURST OF 2 PIPELINED SRAM WITH QDR TM ARCHITECTURE (PRELIMINARY) Sunset Owner: Jayasree Nayar (NJY) Replaced by: NONE PRELIMINARY CY7C1306CV25 18-Mbit Burst of 2 Pipelined SRAM with

Contextual Info: PRELIMINARY CY7C1306CV25 18-Mbit Burst of 2 Pipelined SRAM with QDR Architecture Features Functional Description n Separate independent read and write data ports p Supports concurrent transactions n 167 MHz clock for high bandwidth p 2.5 ns Clock-to-Valid access time