CY7C1268V18 Search Results

CY7C1268V18 Datasheets (4)

Part	ECAD Model	Manufacturer	Description	Datasheet Type	PDF	PDF Size	Page count
CY7C1268V18		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)	Original	PDF	1.09MB	27
CY7C1268V18-300BZC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)	Original	PDF	448.75KB	27
CY7C1268V18-333BZC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)	Original	PDF	448.75KB	27
CY7C1268V18-400BZXC		Cypress Semiconductor	36-Mbit DDR-II+ SRAM 2-Word Burst Architecture (2.5 Cycle Read Latency)	Original	PDF	448.75KB	27

CY7C1268V18 Price and Stock

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Rochester Electronics LLC CY7C1268V18-400BZXC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1268V18-400BZXC	Tray			11	1 - 10 - 100 $27.30 1000 $27.30 10000 $27.30	Buy Now
Infineon Technologies AG CY7C1268V18-400BZXC IC SRAM 36MBIT PARALLEL 165FBGA
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
DigiKey	CY7C1268V18-400BZXC	Tray			105	1 - 10 - 100 - 1000 $54.61 10000 $54.61	Buy Now
Cypress Semiconductor CY7C1268V18-400BZXC CY7C1268V18-400BZXC
Distributors	Part	Package	Stock	Lead Time	Min Order Qty	Price	Buy
Verical	CY7C1268V18-400BZXC		67		25	1 - 10 - 100 $31.18 1000 $27.89 10000 $26.25	Buy Now
Rochester Electronics	CY7C1268V18-400BZXC		67		1	1 - 10 - 100 $24.94 1000 $22.31 10000 $21.00	Buy Now

CY7C1268V18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY7C1268V18 CY7C1270V18 PRELIMINARY 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth 2-Word burst for reducing address bus frequency	Original	CY7C1268V18 CY7C1270V18 36-Mbit 165-bas	PDF
Contextual Info: CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit	PDF
Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-06347 Spec Title: CY7C1266V18/CY7C1277V18/CY7C1268V18/ CY7C1270V18, 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Sunset Owner: Jayasree Nayar (NJY) Replaced by: None CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18	Original	CY7C1266V18/CY7C1277V18/CY7C1268V18/ CY7C1270V18, 36-Mbit CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18	PDF
tms 980 Contextual Info: CY7C1277V18 CY7C1268V18 CY7C1270V18 PRELIMINARY 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 9, 2M x 18, 1M x 36) • 300 MHz to 400 MHz clock for high bandwidth • 2-Word burst for reducing address bus frequency	Original	CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit CY7C1277V18/CY7C1268V18/CY7C1270V18 tms 980	PDF
CY7C1266V18 Abstract: CY7C1268V18 CY7C1270V18 CY7C1277V18 Contextual Info: CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • • • • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1266V18 CY7C1277V18 CY7C1268V18 CY7C1270V18 36-Mbit CY7C1266V18, CY7C1277V18, CY7C1268V18, CY7C1270V18 CY7C1266V18 CY7C1268V18 CY7C1277V18	PDF
CY7C1266V18 Abstract: CY7C1268V18 CY7C1270V18 CY7C1277V18 Contextual Info: CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit DDR-II+ SRAM 2-Word Burst Architecture 2.5 Cycle Read Latency Features Functional Description • 36-Mbit density (4M x 8, 4M x 9, 2M x 18, 1M x 36) ■ 300 MHz to 400 MHz clock for high bandwidth	Original	CY7C1266V18, CY7C1277V18 CY7C1268V18, CY7C1270V18 36-Mbit CY7C1277V18, CY7C1270V18 CY7C1266V18 CY7C1268V18 CY7C1277V18	PDF