CY7C1231H Search Results
CY7C1231H Datasheets (3)
Part | ECAD Model | Manufacturer | Description | Datasheet Type | PDF Size | Page count | |
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CY7C1231H |
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2-Mbit (128K x 18) Flow-Through SRAM with NoBL Architecture | Original | 539.4KB | 12 | ||
CY7C1231H-133AXC |
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2-Mbit (128K x 18) Flow-Through SRAM with NoBL Architecture | Original | 539.37KB | 12 | ||
CY7C1231H-133AXI |
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2-Mbit (128K x 18) Flow-Through SRAM with NoBL Architecture | Original | 539.37KB | 12 |
CY7C1231H Price and Stock
Rochester Electronics LLC CY7C1231H-133AXCIC SRAM 2MBIT PARALLEL 100TQFP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY7C1231H-133AXC | Tray | 1,809 | 55 |
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Infineon Technologies AG CY7C1231H-133AXCIC SRAM 2MBIT PARALLEL 100TQFP |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY7C1231H-133AXC | Tray | 144 |
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Cypress Semiconductor CY7C1231H-133AXCCY7C1231H-133AXC |
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Distributors | Part | Package | Stock | Lead Time | Min Order Qty | Price | Buy | ||||
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CY7C1231H-133AXC | 1,467 | 57 |
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CY7C1231H-133AXC | 1,809 | 1 |
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Buy Now |
CY7C1231H Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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CY7C1231H
Abstract: CY7C1231H-133AXI
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Original |
CY7C1231H 133-MHz CY7C1231H w28408 CY7C1231H-133AXI | |
Contextual Info: CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Features Functional Description[1] • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ |
Original |
CY7C1231H 133-MHz 100-pin | |
Contextual Info: THIS SPEC IS OBSOLETE Spec No: 001-00207 Spec Title: CY7C1231H 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Sunset Owner: Jayasree Nayar (njy) Replaced by: None CY7C1231H 2-Mbit (128K x 18) Flow-Through SRAM with NoBL™ Architecture Features |
Original |
CY7C1231H CY7C1231H 133-MHz | |
CY7C1231H
Abstract: CY7C1231H-133AXI
|
Original |
CY7C1231H 133-MHz CY7C1231H CY7C1231H-133AXI | |
Contextual Info: CY7C1231H PRELIMINARY 2-Mbit 128K x 18 Flow-Through SRAM with NoBL Architecture Functional Description[1] Features • Can support up to 133-MHz bus operations with zero wait states — Data is transferred on every clock • Pin compatible and functionally equivalent to ZBT™ |
Original |
CY7C1231H 133-MHz 100-MHz 100-lead CY7C1231H |