CY7C1176KV18 Search Results

CY7C1176KV18 Datasheets Context Search

Catalog Datasheet	Type	Document Tags	PDF
Contextual Info: CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency Configurations Features • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:	Original	CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit 550-MHz CY7C1163KV18	PDF
Contextual Info: CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency Features Configurations • Separate independent read and write data ports ❐ Supports concurrent transactions With Read Cycle Latency of 2.5 cycles:	Original	CY7C1161KV18, CY7C1176KV18 CY7C1163KV18, CY7C1165KV18 18-Mbit 550-MHz CY7C1163KV18	PDF
Contextual Info: CY7C1163KV18/CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports	Original	CY7C1163KV18/CY7C1165KV18 18-Mbit 550-MHz CY7C1165KV18	PDF
3M Touch Systems Contextual Info: CY7C1163KV18, CY7C1165KV18 18-Mbit QDR II+ SRAM Four-Word Burst Architecture 2.5 Cycle Read Latency 18-Mbit QDR® II+ SRAM Four-Word Burst Architecture (2.5 Cycle Read Latency) Features Configurations • Separate independent read and write data ports	Original	CY7C1163KV18, CY7C1165KV18 18-Mbit CY7C1163KV18 550-MHz 3M Touch Systems	PDF