CY7B952 Search Results

irf 648

Contextual Info: fax id: 5009 PRELIMINARY C'i- CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Com pliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul) • No output clock “drift” without data transitions

CY7B952

Abstract: G958 PM5343 WAC013
Contextual Info: CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: • No output clock “drift” without data transitions • Link Status Indication — Jitter Generation (<0.01 UI)

CY7B952

Abstract: G958 PM5343 WAC013
Contextual Info: CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: • No output clock “drift” without data transitions • Link Status Indication — Jitter Generation (<0.01 UI)

Contextual Info: CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: • No output clock “drift” without data transitions • Link Status Indication — Jitter Generation (<0.01 UI)

GR-253-CORE

Abstract: nrzi CY7B952 G958 PM5343 WAC013 GR-253 BUT12
Contextual Info: CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: • No output clock “drift” without data transitions • Link Status Indication — Jitter Generation (<0.01 UI)

AN1226

Abstract: CY7B951 CY7B952
Contextual Info: Connecting CY7B951/CY7B952 to 3.3V Framers AN1226 Overview This document describes how to connect the 5V PECL outputs of the CY7B951 or CY7B952 to 3.3V PECL inputs, and also how to connect the 5V PECL inputs of the CY7B951 or CY7B952 to 3.3V PECL outputs of some framer chips.

stm cl-30

Abstract: CY7B952 PM5343 WAC013 7B952
Contextual Info: fax id: 5009 1CY 7B9 52 PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: — Jitter Generation (<0.01 UI) • No output clock “drift” without data transitions

Contextual Info: fax id: 5009 PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features 100K ECL com patible I/O • OC-3 Com pliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul) No output clock “d rift” without data transitions

84-1MISR4

Abstract: CY7B952 EME-6300 sdh markings EME6300
Contextual Info: Cypress Semiconductor Qualification Report QTP# 97092VERSION 1.0 June, 1997 SST SONET/SDH Serial Transceiver CY7B952 SST™ is a trademark of Cypress Semiconductor Corporation Cypress Semiconductor SST™SONET/SDH Serial Transceiver Device: CYB952 Package: SOIC

Contextual Info: fax id: 5009 W CYPRESS PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features No output clock “drift” without data transitions Link Status Indication Fully compliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul)

CY7B952

Abstract: PM5343 WAC013
Contextual Info: fax id: 5009 PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features • 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifications on: — Jitter Generation (<0.01 UI) • No output clock “drift” without data transitions

sptx

Abstract: zero crossing detector using psoc
Contextual Info: CY7B952 SST SONET/SDH Serial Transceiver SST™ SONET/SDH Serial Transceiver Features • No output clock “drift” without data transitions OC-3 Compliant with Bellcore and CCITT ITU specifications on: ❐ Jitter Generation (<0.01 UI) ❐ Jitter Transfer (<130 kHz)

84-1MISR4

Abstract: CY7B952 EME-6300 JESD22
Contextual Info: Cypress Semiconductor Qualification Report QTP# 96295 VERSION 1.0 May, 1997 SST SONET/SDH Serial Transceiver CY7B952 SST™ is a trademark of Cypress Semiconductor Corporation Cypress Semiconductor SST™SONET/SDH Serial Transceiver Device: CYB952 Package: SOIC

1uF CAPACITOR

Abstract: CY7B952 .1uf capacitor
Contextual Info: CY7B952 Layout Recommendation 2. Use at least a 220-pF and 0.1-µF capacitor to bypass high frequency noise and to satisfy the devices’s instantaneous current needs. Purpose This document provides a layout recommendation for the CY7B952 Clock and Data Recovery chip. A CY7B952 requires a 301kΩ resistor in parallel with a 1-µF capacitor

CY7B952

Abstract: G958 PM5343 WAC013
Contextual Info: fax id: 5009 ' ' ' ' : : S. : : : : : : : : : : CY7B952 .PRELIMINARY W OYPHESS SST SONET/SDH Serial Transceiver Features • 10 0K E C L c o m p a tib le I/O • O C -3 C o m p lia n t w ith B ellco re and C C IT T IT U sp e c ifi­

stm cl-30

Abstract: WAC013 CY7B952 PM5343
Contextual Info: PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features • No output clock “drift” without data transitions • OC-3 Compliant with Bellcore and CCITT ITU specifications on: — Jitter Generation (<0.01 UI) • Link Status Indication • Loop-back testing

Contextual Info: fax id: 5009 W CYPRESS PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver Features 100K ECL com patible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul) No output clock “drift” without data transitions

CY7B952

Abstract: PM5343 WAC013
Contextual Info: PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver CY7B952 • 100K ECL compatible I/O Features • No output clock “drift” without data transitions • OC-3 Compliant with Bellcore and CCITT ITU specifications on: — Jitter Generation (<0.01 UI)

Contextual Info: fax id: 5009 PRELIMINARY CYPRESS CY7B952 SST SONET/SDH Serial Transceiver Features No output clock “drift” without data transitions Link Status Indication Fully compliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul)

CY7B951

Abstract: CY7B952
Contextual Info: fax id: 5127 Connecting CY7B951/CY7B952 to 3.3V Framers Overview are best to see a PECL cross-over at 2.05V. Figure 1b shows the set-up for interfacing the two chips. This document describes how to connect the 5V PECL outputs of the CY7B951 or CY7B952 to 3.3V PECL inputs, and

.1uf capacitor

Abstract: CY7B952 1uF CAPACITOR
Contextual Info: fax id: 5130 CY7B952 Layout Recommendation Purpose 2. Use at least a 220-pF and 0.1-µF capacitor to bypass high frequency noise and to satisfy the devices’s instantaneous current needs. This document provides a layout recommendation for the CY7B952 Clock and Data Recovery chip. A CY7B952 requires a 301kΩ resistor in parallel with a 1-µF capacitor

CY7B952

Abstract: G958 PM5343 WAC013 ir817
Contextual Info: fax id: 5009 PRELIMINARY CY7B952 W CYPRESS SST SONET/SDH Serial Transceiver Features 100K ECL compatible I/O • OC-3 Compliant with Bellcore and CCITT ITU specifi­ cations on: — Jitter Generation (<0.01 Ul) No output clock “drift” without data transitions

CY7C971

Abstract: CY7B951 CY7B952 CY7C955 CY7C923
Contextual Info: PRESS RELEASE CYPRESS DEBUTS BELLCORE-COMPLIANT ATM SONET/SDH TRANCEIVER Meets Tough Jitter Specs With Highly Integrated PLL Technology SAN JOSE, Calif., September 8, 1997 - Cypress Semiconductor today added to its expanding data communications product line with the introduction of the CY7B952

CY7B952

Abstract: PM5343 WAC013
Contextual Info: PRELIMINARY CY7B952 SST SONET/SDH Serial Transceiver CY7B952 • 100K ECL compatible I/O Features • No output clock “drift” without data transitions • OC-3 Compliant with Bellcore and CCITT ITU specifications on: — Jitter Generation (<0.01 UI)