ALVC32 Search Results

74ALVC32

Abstract: 74ALVC32M 74ALVC32MTC M14A MTC14 ALVC32
Contextual Info: Revised February 2002 ALVC32 Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC32 contains four 2-input OR gates. This product is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

74ALVC32

Abstract: 74ALVC32M 74ALVC32MTC M14A MTC14 ALVC32
Contextual Info: Revised September 2001 ALVC32 Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC32 contains four 2-input OR gates. This product is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

74ALVC32

Abstract: 74ALVC32M 74ALVC32MTC J-STD-020B M14A MTC14
Contextual Info: ALVC32 Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs Features General Description • 1.65V to 3.6V VCC supply operation The ALVC32 contains four 2-input OR gates. This product is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

74ALVC32

Abstract: 74ALVC32M 74ALVC32MTC 74ALVC32MTCX M14A MTC14 jedec MO-153
Contextual Info: Revised February 2005 ALVC32 Low Voltage Quad 2-Input OR Gate with 3.6V Tolerant Inputs and Outputs General Description Features The ALVC32 contains four 2-input OR gates. This product is designed for low voltage 1.65V to 3.6V VCC applications with I/O compatibility up to 3.6V.

va32

Abstract: A115-A C101 SN74ALVC32 SN74ALVC32D
Contextual Info: ALVC32 QUADRUPLE 2ĆINPUT POSITIVEĆOR GATE SCES108F − JULY 1997 − REVISED AUGUST 2003 D D D D D D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V Latch-Up Performance Exceeds 250 mA Per

ALVC32

Contextual Info: 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1.27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 40°C to +85°C

A115-A

Abstract: C101 SN74ALVC32 SN74ALVC32D
Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

A115-A

Abstract: C101 SN74ALVC32 SN74ALVC32D VA32
Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

IDT74ALVC32

Abstract: ALVC32
Contextual Info: ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE DESCRIPTION: FEATURES: – – – – – – – – This quadruple 2-input positive-OR gate is built using advanced dual

VA32

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE nicfe/ ALVC32 ADVANCE INFORMATION Integrated Device Technology, Inc. DESCRIPTION: FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

va32

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

ALVC32

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

IDT74ALVC32

Contextual Info: ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE EXTENDED COMMERCIAL TEMPERATURE RANGE ALVC32 ADVANCE INFORMATION 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE DESCRIPTION: FEATURES: – – 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015;

Contextual Info: _ irr R i D E S C R IP T IO N : FEATURES: - 0.5 MICRON CMOS Technology ESD > 2000V per MIL-STD-883, Method 3015; > 200V using machine model C = 200pF, R = 0 1,27mm pitch SOIC, 0.65mm pitch SSOP and 0.65mm pitch TSSOP packages Extended commercial range of - 40° C to +85° C

A115-A

Abstract: C101 SN74ALVC32 SN74ALVC32D
Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V

IDT74ALVC32

Contextual Info: ALVC32 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE INDUSTRIAL TEMPERATURE RANGE 3.3V CMOS QUADRUPLE 2-INPUT POSITIVE-OR GATE ALVC32 FEATURES: DESCRIPTION: • 0.5 MICRON CMOS Technology • ESD > 2000V per MIL-STD-883, Method 3015; > 200V using

A115-A

Abstract: C101 SN74ALVC32 SN74ALVC32D
Contextual Info: ALVC32 QUADRUPLE 2-INPUT POSITIVE-OR GATE www.ti.com SCES108G – JULY 1997 – REVISED NOVEMBER 2004 FEATURES • • • • • D, DGV, NS, OR PW PACKAGE TOP VIEW Operates From 1.65 V to 3.6 V Max tpd of 2.8 ns at 3.3 V ±24-mA Output Drive at 3.3 V