96ms/bit, datasheet & application notes

Part	Manufacturer	Description
SN74AXC2T45DCTR	Texas Instruments	Dual-bit dual-supply bus transceiver with configurable voltage translation
SN74AXC2T45DCUR	Texas Instruments	Dual-bit dual-supply bus transceiver with configurable voltage translation
SN74AXC1T45DCKR	Texas Instruments	Single-bit dual-supply bus transceiver 6-SC70 -40 to 125
SN74AXC1T45DBVR	Texas Instruments	Single-bit dual-supply bus transceiver 6-SOT-23 -40 to 125
SN74AXC1T45DTQR	Texas Instruments	Single-bit dual-supply bus transceiver 6-X2SON -40 to 125
SN74LVC2T45QDCURQ1	Texas Instruments	Automotive Catalog Dual-Bit Dual Supply Transceiver with Configurable Voltage Translation 8-VSSOP -40 to 125

96ms/bit, Datasheets Context Search

Catalog Datasheet	MFG & Type	PDF	Document Tags
2006 - AN-1451 Abstract: LM4935 AN1451 0X08H Text: ) NOISE_GATE_ON ( bit 4(0x08h) AGC 6dB 36dB 2dB NOISE_GATE_THRES AGC_TIGHT ( bit 7(0x09h	Original	PDF	LM4935 AN-1451 AN201847 -12dBFS 14dBFS 0x07h) A04/24/06 AN-1451 LM4935 AN1451 0X08H
2006 - "Microphone Preamplifier" Abstract: "Microphone Preamplifier" agc variable gain audio preamplifier Microphone Preamplifier high gain microphone preamplifier AN-1451 noise gate LM4935 AN1451 The microphone preamplifier Text: algorithm. It informs the AGC circuit about the closest expected ADC sample rate. This bit does not set , to 36dB in 2dB steps. NOISE_GATE_ON ( bit 4(0x08h) Setting this bit will mute cause the amplifier , . AGC_TIGHT ( bit 7(0x09h) Setting this bit allows the AGC gain algorithm to control the microphone , stages or as an input signal for the ADC. When the analog path is used, this bit should be cleared. This , routed to the ADC for recording or playback, the AGC_TIGHT bit should be set to ensure that the audio	Original	PDF	LM4935 CSP-9-111S2) CSP-9-111S2. AN-1451 "Microphone Preamplifier" "Microphone Preamplifier" agc variable gain audio preamplifier Microphone Preamplifier high gain microphone preamplifier AN-1451 noise gate AN1451 The microphone preamplifier
1998 - 31200 Abstract: No abstract text available Text: APPLICATION NOTE NOTES ON USING THE ST623XB/ST628XB UART by 8- bit Micro Application Team 1 AVOIDING A SPURIOUS INTERRUPT DURING RESET Care must be taken if during RESET, the reception RXD/PD4 line , will be acknowledged by the UART cell as a valid receive start bit . 88 UART clocks ( 8 clocks per bit ) are then needed to receive one burst of 11 bits (1 start bit + 8 bit data + 1 parity bit + 1 stop bit , operating Baud rate ( bit BR2.BR0 of UART Control Register). The following tables show the required timing	Original	PDF	ST623XB/ST628XB 31200
dac 0803 Abstract: sinus wave oscillator AN913 ST62 sinus pwm Text: AN913 APPLICATION NOTE PWM GENERATION WITH THE ST62 16- BIT AUTO-RELOAD TIMER by 8- bit Micro Application Team INTRODUCTION This note presents how to use the ST62 16- bit Auto-Reload Timer (ARTimer , PWM output pin generates a DTMF to dial a telephone number. 1 16- BIT AUTO-RELOAD TIMER DESCRIPTION This timer is a 16- bit downcounter timer with prescaler (see Figure 1.). It includes auto-reload PWM , by the following registers: Status control registers (8- bit ) SCR1, SCR2, SCR3, SCR4 CP Capture	Original	PDF	AN913 16-BIT 16-bits dac 0803 sinus wave oscillator AN913 ST62 sinus pwm
1998 - 31200 Abstract: No abstract text available Text: APPLICATION NOTE R NOTES ON USING THE ST623XB/ST628XB UART by 8- bit Micro Application Team , falling edge will be acknowledged by the UART cell as a valid receive start bit . 88 UART clocks ( 8 clocks per bit ) are then needed to receive one burst of 11 bits (1 start bit +8 bit data+1 parity bit +1 stop bit ). The Receive Interrupt flag RXRDY (bit7 of UART Control Register) is set to 1 after all 11 , operating Baud rate ( bit BR2.BR0 of UART Control Register). The following tables show the required timing	Original	PDF	ST623XB/ST628XB 31200
1998 - sinus wave oscillator Abstract: No abstract text available Text: APPLICATION NOTE PWM GENERATION WITH THE ST62 16- BIT AUTO-RELOAD TIMER by 8- bit Micro Applicatio n Team 1 INTRODUCTION This note presents how to use the ST62 16- bit Auto-Reload Timer (ARTimer , PWM output pin generates a DTMF to dial a telephone number. 2 16- BIT AUTO-RELOAD TIMER DESCRIPTION This timer is a 16- bit downcounter timer with prescaler (see Figure 1.). It includes auto-reload PWM , by the following registers: Status control registers (8- bit ) SCR1, SCR2, SCR3, SCR4 CP Capture	Original	PDF	16-BIT 16-bits sinus wave oscillator
NE5750 Abstract: NE5751 NE5751D NE5751N NES751 SA5750 SA5751 SA5751D SA5751N 100hz anti alias lowpass filter Text: minimum input HIGH voltage, 3.0V. BIT TRANSFER One data bit is transferred during each clock pulse. The , eight bits is followed by one acknowledge bit The acknowledge bit is a HIGH level put on the bus by the , bits in the serial mode where the least significant bit is selectable by hardware on input AO and the , and Test Register MSB LSB PDW T1T7 DEE PRE V1 V2 V3 V4 V4 is volume control bit 4. This is the MSB. A zero is 16dB attenuation V3 is volume control bit 3. Azerois8dB attenuation. V2 is volume	OCR Scan	PDF	NE/SA5751 NE/SA5751 300-3000Hz) SA5751 SA5750 00fl3nafl 7110fl2ti NE5750 NE5751 NE5751D NE5751N NES751 SA5750 SA5751D SA5751N 100hz anti alias lowpass filter
1998 - ST62 Abstract: sinus wave oscillator Text: APPLICATION NOTE R PWM GENERATION WITH THE ST62 16- BIT AUTO-RELOAD TIMER by 8- bit Micro Application Team 1 INTRODUCTION This note presents how to use the ST62 16- bit Auto-Reload Timer (ARTimer , PWM output pin generates a DTMF to dial a telephone number. 2 16- BIT AUTO-RELOAD TIMER DESCRIPTION This timer is a 16- bit downcounter timer with prescaler (see Figure 1). It includes auto-reload PWM , by the following registers: Status control registers (8- bit ) SCR1, SCR2, SCR3, SCR4 CP Capture	Original	PDF	16-BIT 16-bits ST62 sinus wave oscillator
SCL 1058 Abstract: 100hz anti alias lowpass filter 300Hz-3kHz NE5750 BPF filter rf SA5750 SA5751 SA5751D SA5751N SR00656 Text: not busy. BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA , acknowledge bit . The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master , Control and Test Register MSB PDW T1T7 DEE PRE V1 V2 V3 LSB V4 V4 is volume control bit 4. This is the MSB. A zero is 16dB attenuation. V3 is volume control bit 3. A zero is 8dB attenuation. V2 is volume control bit 2. A zero is 4dB attenuation. V1 is volume control bit 1. A	Original	PDF	NE/SA5751 NE/SA5751 300-3000Hz) SA5751 SA5750 SR00658 SCL 1058 100hz anti alias lowpass filter 300Hz-3kHz NE5750 BPF filter rf SA5750 SA5751D SA5751N SR00656
Not Available Abstract: No abstract text available Text: message is the "master"; and devices which are controlled by the master are the "slaves". BIT TRANSFER One data bit is transferred during each clock pulse. The data on the SDA line must remain stable , bits is followed by one acknowledge bit . The acknowledge bit is a HIGH level put on the bus by the , NE5751 is always a slave receiver in the l2C bus configuration (R/W bit -0). The slave address consists of seven bits in the serial mode where the least significant bit is selectable by hardware on input AO and	OCR Scan	PDF	NE/SA5751 ESA5751
Not Available Abstract: No abstract text available Text: are the "slaves". BIT TRANSFER One data bit is transferred during each clock pulse. The data on , transmitter to receiver is not limited. Each byte of eight bits is followed by one acknowledge bit . The acknowledge bit is a HIGH level put on the bus by the transmitter whereas the master generates an extra , configuration (R/W bit -0). The slave address consists of seven bits in the serial mode where the least significant bit is selectable by hardware on input AO and the other more significant bits are internally fixed	OCR Scan	PDF	NE/SA5751 NE/SA5751
NE5751 Abstract: NE5751D NE5751N NES751 SA5750 SA5751 SA5751D SA5751N 100hz anti alias lowpass filter Text: voltage, 1.5V and minimum input HIGH voltage, 3.0V. BIT TRANSFER One data bit is transferred during each , is followed by one acknowledge bit The acknowledge bit is a HIGH level put on the bus by the , bits in the serial mode where the least significant bit is selectable by hardware on input AO and the , and Test Register MSB LSB PDWT1T7DEE PRE V1 V2 V3 V4 V4 is volume control bit 4. This is the MSB. Azero Is 16dB attenuation V3 is volume control bit3. Azero is8dB attenuation. V2 is volume control bit	OCR Scan	PDF	NE/SA5751 NE/SA5751 3000Hz) SA5751 SA5750 7110fl2t, NE5751 NE5751D NE5751N NES751 SA5750 SA5751D SA5751N 100hz anti alias lowpass filter
2001 - LB 1639 Abstract: hl 1628 lcd 3310 SM5128A1CBCMOS-LSIPLLUSA VSOP 28 SM5128A1 SM5128A1N SM5128A1V LB 1649 lcd 5421 Text: No file text available	Original	PDF	SM5128A1 SM5128A1CBCMOS-LSIPLLUSA 24MHz 28pinVSOP, 28pin SM5128A1V SM5128A1N LB 1639 hl 1628 lcd 3310 SM5128A1CBCMOS-LSIPLLUSA VSOP 28 SM5128A1 SM5128A1N SM5128A1V LB 1649 lcd 5421
Not Available Abstract: No abstract text available Text: Fig.1 â¢O p e ra tio n notes Serial transmission Serial data are 16- bit data used to control the	OCR Scan	PDF	BU9262FS BU9262FS 20pin SSOP-A32

NJU26901 Abstract: 24I2S Text: CLK OUT ADC BIT CLK OUT MASTER CLK OUT 3 4 VDD LRI ANALOG LOUT 8 SDO DATA IN ANALOG ROUT 7 NJU26901 BCKI COUNT[1] VSS BIT CLK IN 6 DAC 0.1uF 10uF	Original	PDF	NJU26901 NJU26901M 48kHz85ms, 32kHz128ms, 96kHz43ms 24I2S 13MHz Fs200kHz) 24bit NJU26901
BU9262FS Abstract: LPF112 VN02 VN03 VN05 VN06 Digital Echo delay 16 Pin ICs BU9262 LPF10 Text: ix CD UJ * o < oc S oc Fig.1 â¢Operation notes Serial transmission Serial data are 16- bit data used	OCR Scan	PDF	BU9262FS BU9262FS SSOP-A32 LPF112 VN02 VN03 VN05 VN06 Digital Echo delay 16 Pin ICs BU9262 LPF10
MM3280J05 Abstract: MM3280H02 MM3280G02RRE Text: No file text available	Original	PDF	MM3280 MM3280J05 MM3280H02 MM3280G02RRE
BU9262FS Abstract: VN02 VN03 VN05 VN06 Text: 16- bit data used to control the settings. The signal is input with the rise of SCK. Input data are	OCR Scan	PDF	BU9262FS BU9262FS VN02 VN03 VN05 VN06
Digital Echo delay 16 Pin ICs Abstract: BU9262 2.1 surround sound circuits "DIGITAL ECHO" Text: transmission Serial data are 16- bit data used to control the settings. The signal is input with the rise of SCK	OCR Scan	PDF	BU9262FS BU9262FS 20pin Digital Echo delay 16 Pin ICs BU9262 2.1 surround sound circuits "DIGITAL ECHO"
2012 - MM3280J05 Abstract: MM3280F02RRE MM3280J05NRH MM3280H01NRH MM3280P09RRE MM3280 MM3280G01RRE MM3280T02RRE MM3280H02NRH battery protection ic Text: No file text available	Original	PDF	MM3280 MM3280J05 MM3280F02RRE MM3280J05NRH MM3280H01NRH MM3280P09RRE MM3280G01RRE MM3280T02RRE MM3280H02NRH battery protection ic
2013 - MM3280J05 Abstract: MM3280T02 MM3280H01NRH MM3280H02NRH MM3280C01 4280 MM3280H02 MM3280G02RRE MM3280J05NRH Text: No file text available	Original	PDF	MM3280 MM3280J05 MM3280T02 MM3280H01NRH MM3280H02NRH MM3280C01 4280 MM3280H02 MM3280G02RRE MM3280J05NRH
2006 - AUDIO DELAY CIRCUIT DIAGRAM Abstract: No abstract text available Text: Digital Audio Format Audio Bit Clock (BCK) Frequency Package Power Supply : : : : : 1 Input port / 1 , BCKI I Bit Clock Input 4 VSS G GND 5 COUNT[0] I* Delay Time Control 0 6 COUNT[1] I* Delay Time Control , (#3) is bit clock input pin. This BCKI clock frequency is 64 times as large as the input audio signal , ANALOG LIN DATA OUT ANALOG RIN LR CLK OUT 1 SDI 2 VDD 8 ANALOG LOUT DATA IN ANALOG ROUT BIT CLK IN 6 LRI 7 SDO ADC BIT CLK OUT MASTER CLK OUT 3 NJU26901 BCKI COUNT[1] VSS COUNT[0] DAC	Original	PDF	NJU26901 NJU26901 NJU26901E2 NJU26901M 85msec 48kHz 128msec 32kHz 43msec AUDIO DELAY CIRCUIT DIAGRAM
2004 - AUDIO DELAY CIRCUIT DIAGRAM Abstract: No abstract text available Text: Format Audio Bit Clock (BCKI) Frequency Package Power Supply : : : : : 1 Input port / 1 Output port I2S , . Symbol I/O Description 1 SDI I Audio Data Input 2 LRI I LR Clock Input 3 BCKI I Bit Clock Input 4 VSS G , data are left channel data. LRI="High" shows SDI and SDO data are right channel data. · BCKI(#3) is bit , 2.5V ANALOG LIN DATA OUT ANALOG RIN BIT CLK OUT 2 BCKI 3 SDO 6 0.1uF 5 VSS COUNT[0] MASTER CLK IN 10uF 1 SDI VDD 7 BIT CLK IN 8 DATA IN ANALOG ROUT ANALOG LOUT ADC LR CLK OUT MASTER CLK OUT	Original	PDF	NJU26901 NJU26901 NJU26901E2 85msec 48kHz 128msec 32kHz 43msec 96kHz) AUDIO DELAY CIRCUIT DIAGRAM
2004 - AUDIO DELAY CIRCUIT DIAGRAM Abstract: No abstract text available Text: Format Audio Bit Clock (BCK) Frequency Package Power Supply : : : : : 1 Input port / 1 Output port I2S , . Symbol I/O Description 1 SDI I Audio Data Input 2 LRI I LR Clock Input 3 BCKI I Bit Clock Input 4 VSS G , data are left channel data. LRI="High" shows SDI and SDO data are right channel data. · BCKI(#3) is bit , 2.5V ANALOG LIN DATA OUT ANALOG RIN LR CLK OUT 1 SDI 2 VDD 8 ANALOG LOUT DATA IN ANALOG ROUT BIT CLK IN 6 LRI 7 SDO ADC BIT CLK OUT MASTER CLK OUT 3 NJU26901 BCKI COUNT[1] VSS COUNT[0	Original	PDF	NJU26901 NJU26901 NJU26901E2 85msec 48kHz 128msec 32kHz 43msec 96kHz) AUDIO DELAY CIRCUIT DIAGRAM
2004 - AUDIO DELAY CIRCUIT DIAGRAM Abstract: analog audio delay delaytime 69mS NJU26901 NJU26901E2 audio delay AUDIO interface CIRCUIT DIAGRAM Text: Interface Digital Audio Format Audio Bit Clock (BCK) Frequency Package Power Supply Ver , /O Description 1 SDI I Audio Data Input 2 LRI I LR Clock Input 3 BCKI I Bit Clock Input , channel data. LRI="High" shows SDI and SDO data are right channel data. · BCKI(#3) is bit clock input , diagram 2.5V ANALOG LIN DATA OUT ANALOG RIN 1 SDI 2 LR CLK OUT ADC BIT CLK OUT MASTER , BCKI COUNT[1] VSS BIT CLK IN 6 DAC 0.1uF 10uF COUNT[0] LR CLK IN 5 MASTER	Original	PDF	NJU26901 NJU26901 NJU26901E2 85msec 48kHz 128msec 32kHz 43msec 96kHz) AUDIO DELAY CIRCUIT DIAGRAM analog audio delay delaytime 69mS NJU26901E2 audio delay AUDIO interface CIRCUIT DIAGRAM

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96ms/bit, Datasheets

Top Results (6)

96ms/bit, Datasheets Context Search

2006 - AN-1451

2006 - "Microphone Preamplifier"

1998 - 31200

dac 0803

1998 - 31200

1998 - sinus wave oscillator

NE5750

1998 - ST62

SCL 1058

Not Available

Not Available

NE5751

2001 - LB 1639

Not Available

NJU26901

BU9262FS

MM3280J05

BU9262FS

Digital Echo delay 16 Pin ICs

2012 - MM3280J05

2013 - MM3280J05

2006 - AUDIO DELAY CIRCUIT DIAGRAM

2004 - AUDIO DELAY CIRCUIT DIAGRAM

2004 - AUDIO DELAY CIRCUIT DIAGRAM

2004 - AUDIO DELAY CIRCUIT DIAGRAM