8B10B IC Search Results

8B10B ansi encoder

Abstract: encoder verilog coding verilog hdl code for encoder Altera 8b10b EP1S25F780C5 8B10B EP1C20F400C6 keyboard encoder sun 5 to 32 decoder using 3 to 8 decoder vhdl code EP20K
Contextual Info: 8B10B Encoder/Decoder MegaCore Function User Guide 101 Innovation Drive San Jose, CA 95134 408 544-7000 www.altera.com Core Version: Document Version: Document Date: 1.3.2 1.3.2 rev1 December 2002 Copyright 8B10B Encoder/Decoder MegaCore Function User Guide

PM7354

Abstract: DSLAM config ip pm8374a PM8374
Contextual Info: PM7354 S/UNI Duplex GE Preview Monolithic IC for ATM to Ethernet Interworking at GE Wire Speed FEATURES INTERFACES • Dual fully integrated, 1.25Gbit/s, 8B10B encoded 4-wire LVDS SERDES interface for connecting the internal GE MACs directly to a high-speed,

AVAGO phy

Contextual Info: SPFEIM100_G Fiber Optic Transceiver For Fast Ethernet Data Sheet Description Features The 8-pin Optical Transceiver is a highly integrated CMOS IC combined with a high speed photodiode and LED designed to receive and transmit up to 125Mbit/s optical data which can be 4b5b or 8b10b coded up to 125Mbit/

64B66B

Abstract: Signal Path designer
Contextual Info: 19-2713; Rev 1; 11/03 KIT ATION EVALU E L B AVAILA 12.5Gbps Settable Receive Equalizer Features ♦ Compensates Up to 30in 0.75m of 6-mil FR-4 Transmission Line Loss ♦ 115mW Operating Power ♦ Up to 12.5Gbps Data Rate ♦ Compatible with 8B10B, 64B66B, and PRBS Data

5GHz operational amplifier

Abstract: 10gbps serdes 8B10B MAX3804 MAX3804ETE MO220 Signal Path designer
Contextual Info: 19-2713; Rev 1; 11/03 KIT ATION EVALU E L B AVAILA 12.5Gbps Settable Receive Equalizer Features ♦ Compensates Up to 30in 0.75m of 6-mil FR-4 Transmission Line Loss ♦ 115mW Operating Power ♦ Up to 12.5Gbps Data Rate ♦ Compatible with 8B10B, 64B66B, and PRBS Data

permittivity FR 4

Abstract: permittivity FR 4 PCB loss tangent of FR4 T1644-3 MAX3784 MAX3784A MAX3784AUGE MAX3784UGE MAX3784UTE 3EB05
Contextual Info: 19-2565; Rev 4; 10/07 5Gbps PCB Equalizer Features The MAX3784/MAX3784A 5Gbps equalizers provide compensation for transmission-medium losses in up to 40in of FR-4. They are optimized for short-run length and balanced codes such as 8b10b, as found in multiplexed 1.25Gbps Ethernet systems and 4.25Gbps

loss tangent of FR4

Abstract: MAX3784 MAX3784A MAX3784UTE
Contextual Info: 19-2565; Rev 3; 6/05 5Gbps PC Board Equalizer Features The MAX3784/MAX3784A 5Gbps equalizers provide compensation for transmission-medium losses in up to 40in of FR4. They are optimized for short-run length and balanced codes such as 8b10b, as found in multiplexed 1.25Gbps Ethernet systems and 4.25Gbps

8B10B ansi encoder

Abstract: TC260 TOSHIBA standard cell library
Contextual Info: TC260 SD10 1.6/3.2Gb/s Dual Mode SerDes Macros The TC260 SD10 macros enable building high speed interfaces — while consuming a limited number of pins — between integrated circuits ICs implemented in standard cell or as embedded array in Toshiba’s TC260

Velio

Abstract: 8B10B asic 8B10B in serial communication VC1013
Contextual Info: Preliminary Product Summary 2.5 — 3.125 Gbps Four-Lane CMOS SerDes Serializer / Deserializer GENERAL DESCRIPTION The Velio VC1013 is a 4-lane Serializer / Deserializer IC, which operates from 2.5 − 3.125 Gbps, (and half these rates). The device is designed for flexibility; it has

D3318

Contextual Info: 8101/8104 Gigabit Ethernet Controller Technical Manual November 2000 Order Number R14017.A This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

RXD29

Abstract: D3318 216520-4 8B10B ansi encoder
Contextual Info: 8101/8104 Gigabit Ethernet Controller Technical Manual February 2001 Order Number R14017.A This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

sony R04

Abstract: 100BASE-FX 8B10B DA16 TX2 -RX2
Contextual Info: TECHNICAL MANUAL 8101/8104 Gigabit Ethernet Controller November 2001 This document contains proprietary information of LSI Logic Corporation. The information contained herein is not to be used by or disclosed to third parties without the express written permission of an officer of LSI Logic Corporation.

clause 22 phy registers

Abstract: 13007 h3 ali 3602 detail of D 13007 K mca exam date sheet 1000BASE-X DS1005 STS-48
Contextual Info: LatticeSC/M Family flexiPCS Data Sheet DS1005 Version 01.9, December 2008 LatticeSC/M Family flexiPCS Data Sheet Table of Contents December 2008 Introduction to flexiPCS .1-1

sony rxd7

Abstract: w1p13 XMT 2315 8B10B RXD14 3156 00010001
Contextual Info: 8101 8101 Gigabit Ethernet Controller 99110 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

TC260 TOSHIBA standard cell library

Contextual Info: TC260 SD11 1.25/2.5Gb/s Dual Mode SerDes Macros The TC260 SD11 macros enable building high speed interfaces — while consuming a limited number of pins — between integrated circuits ICs implemented in standard cell or as embedded array in Toshiba’s TC260

ACS9010

Abstract: XTAL 32.768MHz 8B10B ACS4050 ACS405CS 3.2768MHz crystal
Contextual Info: ACS405CS Main Features * Full duplex serial transmission through a single fiber-optic cable without the need for expensive WDM devices. AC S4 05 CS 4000 SERIES Acapella Optical Modem IC * E2 data-rates of 8.448Mbps or 4*E1 at 2.048Mbps. T2 data rates of 6.312Mbps or 4*T1 at 1.544Mbps.

bryan adams

Abstract: fg wilson generator prbs using lfsr hyperlynx dell monitor circuit diagram led based graphic equalizer ic matlab Seminar Microwave PIN diode spice 750um Design Seminar Signal Transmission
Contextual Info: DesignCon 2007 Pre-Emphasis and Equalization Parameter Optimization with Fast, WorstCase/Multibillion-Bit Verification Andy Turudic, Altera Corporation aturudic@altera.com Steven McKinney, Mentor Graphics Steven_McKinney@mentor.com Vladimir Dmitriev-Zdorov

TN1176

Abstract: LFE395 alarm clock design of digital verilog IPUG68 CRPAT
Contextual Info:  LatticeECP3 XAUI Demo Design User’s Guide July 2010 UG23_01.2  LatticeECP3 XAUI Demo Design User’s Guide Lattice Semiconductor Introduction This document provides technical information and instructions on using the LatticeECP3 XAUI Demo Design.

XMT 2315

Contextual Info: LOGIC 8101 Gigabit Ethernet Controller 99110 This document is an LSI Logic document. Any reference to SEEQ Technology should be considered LSI Logic. Note: Check for latest Data Sheet revision before starting any designs. SEEQ Data Sheets are now on the Web, access

Contextual Info: m W I— I P< W in o o o Acapella Optical Modem IC ACS405CS Main Features * Full duplex serial transm ission through a single fiber-optic cable w ithout the need for expensive WDM devices. * E2 data-rates of 8.448M bps or 4*E1 at 2.048Mbps. T2 data rates of 6.312M bps or 4*T1 at 1.544Mbps.

GETEK FR4

Abstract: backplane Layout power supply 84HP 8B10B AN249 stub Signal Path Designer
Contextual Info: White Paper Selecting the Correct High Speed Transceiver Solution Introduction Many standards and protocols are now using high speed transceivers SERDES as part of their physical interface. The protocols cover a spectrum of applications including communications, computer, industrial

Contextual Info: LMH0041 ,LMH0051 ,LMH0071 ,LMH0341 LMH0341, LMH0041, LMH0071, LMH0051 3 Gbps, HD, SD, DVB-ASI SDI Deserializer with Loopthrough and LVDS Interface Texas In s t r u m e n t s Literature Number: SNLS272P t Sem iconductor LMH0341, LMH0041, LMH0071, LMH0051

Contextual Info: MegaCore IP Library Release Notes MegaCore IP Library Release Notes 101 Innovation Drive San Jose, CA 95134 www.altera.com RN-IP-13.1 Feedback 2013 Altera Corporation. All rights reserved. ALTERA, ARRIA, CYCLONE, HARDCOPY, MAX, MEGACORE, NIOS, QUARTUS and STRATIX words and logos

XTAL 32.768MHz

Abstract: 8B10B ACS4060 ACS406CS ACS9010 3.2768MHz Crystal 32.768Mhz crystal
Contextual Info: ACS406CS Main Features Full duplex serial transmission through a single fiber-optic cable without the need for expensive WDM devices. * E2 data-rates of 8.448Mbps or 4 * E1 at 2.048Mbps. T2 data rates of 6.312Mbps or 4 * T1 at 1.544Mbps. * 4 clock domains for independent transmission of 4 * E1 or