8B10B ASIC Search Results

Contextual Info: Data Sheet December 1999 CDRM850 850 Mbits/s Multichannel Digital Timing Recovery t f ar Features Description • Receives scrambled serial data at 848 Mbits/s rate or 8b10b encoded serial data at a 850 Mbits/s rate. ■ Also receives and transmits subrate 424 Mbits/s

aircraft logic gates

Abstract: 50944
Contextual Info: ISSP1 High-Speed Interface Family ISSP Series Features continued Description NEC Electronics has expanded the first generation of Instant Silicon Solutions Platform (ISSP™) with the ISSP1 High-Speed Interface (HSI) family, a new class of ASIC device that

8B10B ic

Abstract: 10B8B 8B10B asic 8B10B in serial communication Velio Velio Communications VC1003 8B10B
Contextual Info: Preliminary Product Summary 2.5 — 3.125 Gbps Eight-Lane CMOS SerDes Serializer / Deserializer GENERAL DESCRIPTION The Velio VC1003 is an 8-lane Serializer / Deserializer IC, which operates from 2.5 − 3.125 Gbps, (and half these rates). The device is designed for flexibility; it has

8B10B ansi encoder

Abstract: TC260 TOSHIBA standard cell library
Contextual Info: TC260 SD10 1.6/3.2Gb/s Dual Mode SerDes Macros The TC260 SD10 macros enable building high speed interfaces — while consuming a limited number of pins — between integrated circuits ICs implemented in standard cell or as embedded array in Toshiba’s TC260

Velio

Abstract: 8B10B asic 8B10B in serial communication VC1013
Contextual Info: Preliminary Product Summary 2.5 — 3.125 Gbps Four-Lane CMOS SerDes Serializer / Deserializer GENERAL DESCRIPTION The Velio VC1013 is a 4-lane Serializer / Deserializer IC, which operates from 2.5 − 3.125 Gbps, (and half these rates). The device is designed for flexibility; it has

a1698

Abstract: 8B10B asic nec 928 Cell-based ASIC 8B10B
Contextual Info: ISSP/150 nm ASIC Technology ISSP1 - High-Speed Interface Family Product Letter Description The ISSP1-HSI, the Instant Silicon Solutions PlatformTM ISSP High-Speed Interface (HSI) family, is a new class of ASIC device that features built-in, highspeed Serializer/Deserializer (SerDes) transceiver cores. Ideal for mid-volume

MF Electronics crystal oscillator m1200

Abstract: Photo sensitive diode Siemens diode Ssi K28 0/Siemens diode Ssi K28 d313 TRANSISTOR equivalent 74LS00 ir led PHOTODIODE transistor d313 pinout Analog Applications Journal 10B12B
Contextual Info: a Am79168/Am79169 TAXI -275 T echnical M anual Advanced Micro Devices Am79168/Am79169-275 TAXI-275 Integrated Circuits T e c h n ic a l M a n u a l Rev. 1.0, 1993 A D V A N C E D M I C R O D E V I C E S El 1993 Advanced Micro Devices, Inc. Advanced Micro Devices reserves the right to make changes in its products

64B66B

Abstract: 8B10B in serial communication fiber TRANSCEIVER CIRCUIT DIAGRAM rs232 1000H OC-768 VME64 8B10B asic 8B10B ansi encoder
Contextual Info: White Paper The Evolution of High-Speed Transceiver Technology Introduction The Internet revolution has led to a massive increase in data traffic. This trend is set to continue; over the next few years and it is likely that 95% of all communication traffic will shift to data. The need to support high bandwidth

aircraft logic gates

Abstract: ABGA ASIC, FCBGA
Contextual Info: ISSP1 High-Speed Interface Family ISSP Series Features continued Description With multiple high-speed serializer/deserializer (SerDes) transceiver cores built into the platform, the ISSP1 High-Speed Interface (HSI) family brings fast-throughput capabilities

GETEK FR4

Abstract: backplane Layout power supply 84HP 8B10B AN249 stub Signal Path Designer
Contextual Info: White Paper Selecting the Correct High Speed Transceiver Solution Introduction Many standards and protocols are now using high speed transceivers SERDES as part of their physical interface. The protocols cover a spectrum of applications including communications, computer, industrial

verilog code of 32 bit mac

Abstract: 8B10B MII PHY verilog code for phy interface
Contextual Info: Inventra Soft Core RTL IP PE-GMAC0™ Gigabit Ethernet MAC D A T A S H E E Major Product Features: • Supports 10-bit SERDES or GMII PE-GMAC0 Data Host Data Streams (Tx and Rx) Gigabit Ethernet MAC Host CPU Access Signals Network Device Management Examples:

MAC-1G

Abstract: RTL code for ethernet 1000BASE-X FF1152
Contextual Info: IEEE 802.3-2002 Standard compliance MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer Configurable and monitorable through the Management Interface 1000BASE-X Auto-Negotiation process support for information data exchange with a link partner

TC260 TOSHIBA standard cell library

Contextual Info: TC260 SD11 1.25/2.5Gb/s Dual Mode SerDes Macros The TC260 SD11 macros enable building high speed interfaces — while consuming a limited number of pins — between integrated circuits ICs implemented in standard cell or as embedded array in Toshiba’s TC260

1000BASE-X

Abstract: FF1152 1000base-x xilinx
Contextual Info: IEEE 802.3-2002 Standard compliance MAC-1G-PCS Gigabit Ethernet MAC Controller Physical Coding Sublayer Configurable and monitorable through the Management Interface 1000BASE-X Auto-Negotiation process support for information data exchange with a link partner

A4993-02

Abstract: IXF1002 IXF440 1000Base-CX
Contextual Info: Advance Information Brief Datasheet SEPTEMBER 1999 Order Number: 278309-001 IXP1002 Dual Port Gigabit Ethernet Controller General Description Benefits The IXF1002 Dual Port Gigabit Ethernet Controller includes two full duplex independent 1000-Mb/s Ethernet

LTC6600-20

Abstract: LTC1993 parallel scrambler JESD204 LTC2272 LTC2273 LTC1461-2 LTC6600
Contextual Info: Electrical Specifications Subject to Change LTC2274 16-Bit, 105Msps Serial Output ADC DESCRIPTION FEATURES n High Speed Serial Interface JESD204 Sample Rate: 105Msps 77.7dBFS Noise Floor 100dB SFDR SFDR >82dB at 250MHz (1.5VP-P Input Range) PGA Front End (2.25VP-P or 1.5VP-P Input Range)

"higig header"

Abstract: higig specification higig protocol overview TN1154 cx4 to sma BCM56802 higig pause frame ir9216 BROADCOM higig2
Contextual Info: LatticeSC/M Broadcom HiGig+ 12 Gbps Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1154 Introduction This technical note describes a physical layer HiGig+ 12 Gbps interoperability test between a LatticeSC/M device and the Broadcom BCM56802 network switch. The test was limited to the physical layer up to XGMII of the 10

BCM8228

Abstract: STM-16
Contextual Info: BCM8228 VARIRATE MULTI-RATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PM SUMMARY OF BENEFITS FEATURES • Highly integrated rate adaptation device that maps a single STS-3/ STM-1 or a single STS-12/STM-4 stream into STS-48/STM-16 frames • Channel Add/Channel Extract functionality for mapping and

Contextual Info: BCM8228 PRODUCT Brief VariRateTM MULTI-RATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PM B C M 8 2 2 8 F E AT U R E S Highly integrated rate adaptation device that maps a • single STS-3/STM-1 or a single STS-12/STM-4 stream • • • • • • •

Contextual Info: LatticeECP5 Family Handbook HB1012 Version 01.0, March 2014 Table of Contents LatticeECP5 Family Handbook Section I. LatticeECP5 Family Data Sheet Introduction Features . 1-1

BCM56800

Abstract: higig specification ethernet BCM Gigabit LFSC3GA25E 1000BASE-X higig pause frame cx4 to sma bcm pause frame 1gbps serdes
Contextual Info: LatticeSC/M Broadcom 1-Gigabit Ethernet Physical Layer Interoperability Over CX-4 August 2007 Technical Note TN1157 Introduction This technical note describes a 1000BASE-X physical layer Gigabit Ethernet interoperability test between a LatticeSC/M device and the Broadcom BCM56800 network switch. The test was limited to the physical layer up to

Contextual Info: BCM8228 VARIRATE MULTIRATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PERFORMANCE MONITORING SUMMARY OF BENEFITS FEATURES • Highly-integrated rate-adaptation device that maps a single STS-3/ STM-1 or a single STS-12/STM-4 stream into STS-48/STM-16 frames.

BCM8228

Abstract: OC48 STM-16 STS-48
Contextual Info: BCM8228 VARIRATE MULTIRATE TRANSCEIVER WITH SONET RATE ADAPTATION AND PERFORMANCE MONITORING SUMMARY OF BENEFITS FEATURES • Highly integrated rate-adaptation device that maps a single STS-3/ STM-1 or a single STS-12/STM-4 stream into STS-48/STM-16 frames

0530H

Abstract: TO840 10-lane LM97600 50vias UFH292A
Contextual Info: LM97600 7.6-Bit, 1/2/4 Channel, 5/2.5/1.25 GSPS, High Performance, Low Power A/D Converter General Description Features The LM97600 is a single/dual/quad, low power, high performance SiGe BiCMOS analog-to-digital converter that digitizes signals at sampling rates up to 5.0/2.5/1.25 GSPS.