84 PIN CPU Search Results

Contextual Info: M32C/84 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/84 is a single-chip microcomputer that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/84 group is available in 144-pin and 100-pin plastic molded

BCRT-30

Abstract: 12MHZ 1553B UT1553B MIL-STD-1553B D1398
Contextual Info: UT1553B BCRT ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553B dual-redundant ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT mode ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

UT1553BCRTM

Abstract: 265u 11TA31 UT1553 UT1553B rta2
Contextual Info: UT1553 BCRTM ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553 dual-redundant Bus ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT and M modes ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

P113

Abstract: P114 P115 Z87000 Z87010 Z87L00
Contextual Info: PRELIMINARY PRODUCT SPECIFICATION 1 Z87000/Z87L00 1 SPREAD SPECTRUM CONTROLLERS FEATURES Device ROM KWords RAM* I/O (Words) Lines Z87000 12 512 32 Z87L00 12 512 32 Package Information • 84-Pin PLCC 100-Pin QFP 100-Pin QFP Note: *General-Purpose ■ ■

P110

Abstract: P111 P112 P113 P114 P115 Z87000 Z87010 CP FSK modulator and Demodulator SPREAD-SPECTRUM SYSTEM
Contextual Info: PRELIMINARY PRODUCT SPECIFICATION 1 Z87000 1 SPREAD-SPECTRUM CONTROLLER FEATURES Device ROM KWords Z87000 12 RAM* I/O (Words) Lines 512 32 – Package Information 84-Pin PLCC 100-Pin QFP • Note: *General-Purpose ■ ■ User-Modifiable Features Software

Cordless Phone system block diagram

Abstract: Transceiver Base Station TDD Cordless telephone system block diagram TDD synchronizer frequency hopping spread spectrum 900 Cordless Phone block diagram Z87000 Z87010 fsk modulator Transceiver TDD
Contextual Info: 1 Z87000 1 SPREAD-SPECTRUM CONTROLLER FEATURES Device ROM KWords Z87000 12 RAM* I/O (Words) Lines 512 32 – Package Information 84-Pin PLCC 100-Pin QFP • Note: *General-Purpose ■ ■ User-Modifiable Features Software Governs Phone Transceiver Circuitry Provides Primary Cordless Phone

EQUIVALENT TIMER IC WITH CD 4060

Abstract: 5q-5g 84 pin plcc ic base R3041
Contextual Info: IDT79R3041 IDT79RV3041 IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS Double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls

Contextual Info: IDT79R3041 IDT79RV3041 IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS Double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls

Multibus ii protocol

Abstract: Multibus arbitration protocol 486 system bus
Contextual Info: TO SHIBA INTEGRATED CIRCUIT BAC TECHNICAL D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION ' The MULTIBUS II Bus Arbiter/Contro1ler (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

MIPS R3051

Contextual Info: Integrated Device Technology, Inc. Single, double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls On-chip 4-word read buffer supports burst or simple block

Contextual Info: AT43216 Features • One-Chip SCSI-2 Fast Architecture Controller for Host and 8-blt or 16-btt Peripheral Applications • 84-Pin PLCC Package, Sub-Micron CMOS Technology • Supports ANSI X3T9.2 SCSI Standard, with SCSI-2 Fast Architecture • Functions as an Initiator or a Target

Contextual Info: df) IDT79R3041 INTEGRATED RISController™ FOR LOW-COST SYSTEMS ADVANCE ,NFX ? S ïïi2 ï In te g ra te d Dev Ic e T ec hnology, In c . FEATURES: Single, double-frequency clock input 16 and 20MHz operation 14 MIPS at 20MHz Low cost 84-pin PLCC packaging

Multibus ii protocol

Abstract: Multibus arbitration protocol
Contextual Info: TOSHIBA INTEGRATED CIRCUIT BAC 8 4 1 1 0 TE C H N IC A L D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION The MULTIBUS II Bus Arbiter/Controller (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

Contextual Info: Integrated Device Technology, Inc* Single, double-frequency clock input 16.67MHz, 20MHz, 25M Hz and 33MHz operation 16MIPS a t2 0M H z Low cost 84-pin PLCC packaging O n-chip 4-deep write buffer elim inates memory write stalls O n-chip 4-word read buffer supports burst o r sim ple block

20890

Contextual Info: FUJITSU SEMICONDUCTOR DATA SHEET DS05-20890-1E PAGE MODE FLASH MEMORY CMOS 32 M 2 M x 16/1 M × 32 BIT MBM29PL3200TE/BE 70/90 • DESCRIPTION The MBM29PL3200TE/BE is 32 M-bit, 3.0 V-only Page mode Flash memory organized as 2 M words of 16 bits each or 1 M words of 32 bits each. The device is offered in 90-pin SSOP and 84-ball FBGA packages. This device

R5F35L26

Abstract: R5F3562EDFE R5F35623 D56Eh D625h
Contextual Info: Datasheet M16C/5LD Group, M16C/56D Group RENESAS MCU 1. R01DS0132EJ0120 Rev.1.20 Nov 25, 2011 Overview 1.1 Features The M16C/5LD and M16C/56D Group’s microcomputers MCUs are single-chip control units that utilize high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5LD and

ARM9

Abstract: ARM968E-S LPC2923 LQFP100 ARMv5TE
Contextual Info: LPC2921/2923/2925 ARM9 microcontroller with CAN, LIN, and USB Rev. 03 — 14 April 2010 Product data sheet 1. General description The LPC2921/2923/2925 combine an ARM968E-S CPU core with two integrated TCM blocks operating at frequencies of up to 125 MHz, Full-speed USB 2.0 device controller,

R5F35L2EDFE

Contextual Info: Datasheet M16C/5LD Group, M16C/56D Group RENESAS MCU 1. R01DS0132EJ0120 Rev.1.20 Nov 25, 2011 Overview 1.1 Features The M16C/5LD and M16C/56D Group’s microcomputers MCUs are single-chip control units that utilize high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5LD and

102 m x1 y1

Abstract: 100P6S-A M3081NMC-XXXGP
Contextual Info: M32C/81 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER REJ03B0031-0020Z Rev.0.20 1 Jul., 2003 1. Overview The M32C/81 is single-chip microcomputer that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/81 group is available in the 144-pin and 100-pin plastic

M30621MCP-XXXGP

Abstract: M30622MEP-XXXFP M30622MEP M30622F8PGP M16C M30626FHPFP M30622M6P-XXXFP M30622M6P-XXXGP M30622M8P-XXXFP M30623M6P-XXXGP M30624MGP-XXXFP
Contextual Info: M16C/62 Group M16C/62P, M16C/62PT SINGLE-CHIP 16-BIT CMOS MICROCOMPUTER REJ03B0001-0210Z Rev.2.10 Nov. 07, 2003 1. Overview The M16C/62 group (M16C/62P, M16C/62PT) of single-chip microcomputers are built using the high-performance silicon gate CMOS process using a M16C/60 Series CPU core and are packaged in a 80-pin,

Contextual Info: Datasheet RX610 Group Datasheet RENESAS 32-Bit MCU 1. Overview 1.1 Features R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with

Contextual Info: STM32F401xB STM32F401xC ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 256KB Flash/64KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator™ allowing 0-wait state execution

Contextual Info: STM32F401xD STM32F401xE ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator allowing 0-wait state execution

Contextual Info: STM32F401xD STM32F401xE ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator™ allowing 0-wait state execution