84 PIN CPU Search Results

UT1553BCRTM

Abstract: 265u 11TA31 UT1553 UT1553B rta2
Contextual Info: UT1553 BCRTM ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553 dual-redundant Bus ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT and M modes ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

P110

Abstract: P111 P112 P113 P114 P115 Z87000 Z87010 CP FSK modulator and Demodulator SPREAD-SPECTRUM SYSTEM
Contextual Info: PRELIMINARY PRODUCT SPECIFICATION 1 Z87000 1 SPREAD-SPECTRUM CONTROLLER FEATURES Device ROM KWords Z87000 12 RAM* I/O (Words) Lines 512 32 – Package Information 84-Pin PLCC 100-Pin QFP • Note: *General-Purpose ■ ■ User-Modifiable Features Software

Cordless Phone system block diagram

Abstract: Transceiver Base Station TDD Cordless telephone system block diagram TDD synchronizer frequency hopping spread spectrum 900 Cordless Phone block diagram Z87000 Z87010 fsk modulator Transceiver TDD
Contextual Info: 1 Z87000 1 SPREAD-SPECTRUM CONTROLLER FEATURES Device ROM KWords Z87000 12 RAM* I/O (Words) Lines 512 32 – Package Information 84-Pin PLCC 100-Pin QFP • Note: *General-Purpose ■ ■ User-Modifiable Features Software Governs Phone Transceiver Circuitry Provides Primary Cordless Phone

EQUIVALENT TIMER IC WITH CD 4060

Abstract: 5q-5g 84 pin plcc ic base R3041
Contextual Info: IDT79R3041 IDT79RV3041 IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS Double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls

Contextual Info: IDT79R3041 IDT79RV3041 IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS Double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls

Multibus ii protocol

Abstract: Multibus arbitration protocol 486 system bus
Contextual Info: TO SHIBA INTEGRATED CIRCUIT BAC TECHNICAL D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION ' The MULTIBUS II Bus Arbiter/Contro1ler (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

MIPS R3051

Contextual Info: Integrated Device Technology, Inc. Single, double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls On-chip 4-word read buffer supports burst or simple block

Contextual Info: AT43216 Features • One-Chip SCSI-2 Fast Architecture Controller for Host and 8-blt or 16-btt Peripheral Applications • 84-Pin PLCC Package, Sub-Micron CMOS Technology • Supports ANSI X3T9.2 SCSI Standard, with SCSI-2 Fast Architecture • Functions as an Initiator or a Target

Contextual Info: df) IDT79R3041 INTEGRATED RISController™ FOR LOW-COST SYSTEMS ADVANCE ,NFX ? S ïïi2 ï In te g ra te d Dev Ic e T ec hnology, In c . FEATURES: Single, double-frequency clock input 16 and 20MHz operation 14 MIPS at 20MHz Low cost 84-pin PLCC packaging

Multibus ii protocol

Abstract: Multibus arbitration protocol
Contextual Info: TOSHIBA INTEGRATED CIRCUIT BAC 8 4 1 1 0 TE C H N IC A L D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION The MULTIBUS II Bus Arbiter/Controller (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

Contextual Info: Integrated Device Technology, Inc* Single, double-frequency clock input 16.67MHz, 20MHz, 25M Hz and 33MHz operation 16MIPS a t2 0M H z Low cost 84-pin PLCC packaging O n-chip 4-deep write buffer elim inates memory write stalls O n-chip 4-word read buffer supports burst o r sim ple block

R5F35L26

Abstract: R5F3562EDFE R5F35623 D56Eh D625h
Contextual Info: Datasheet M16C/5LD Group, M16C/56D Group RENESAS MCU 1. R01DS0132EJ0120 Rev.1.20 Nov 25, 2011 Overview 1.1 Features The M16C/5LD and M16C/56D Group’s microcomputers MCUs are single-chip control units that utilize high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5LD and

R5F35L2EDFE

Contextual Info: Datasheet M16C/5LD Group, M16C/56D Group RENESAS MCU 1. R01DS0132EJ0120 Rev.1.20 Nov 25, 2011 Overview 1.1 Features The M16C/5LD and M16C/56D Group’s microcomputers MCUs are single-chip control units that utilize high-performance silicon gate CMOS technology with the M16C/60 Series CPU core. The M16C/5LD and

102 m x1 y1

Abstract: 100P6S-A M3081NMC-XXXGP
Contextual Info: M32C/81 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER REJ03B0031-0020Z Rev.0.20 1 Jul., 2003 1. Overview The M32C/81 is single-chip microcomputer that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/81 group is available in the 144-pin and 100-pin plastic

Contextual Info: Datasheet RX610 Group Datasheet RENESAS 32-Bit MCU 1. Overview 1.1 Features R01DS0097EJ0120 Rev.1.20 Feb 20, 2013 The RX610 Group is an MCU with the high-speed, high-performance RX CPU as its core. One basic instruction is executable in one cycle of the system clock. Calculation functionality is further enhanced, with

Contextual Info: STM32F401xB STM32F401xC ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 256KB Flash/64KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator™ allowing 0-wait state execution

Contextual Info: STM32F401xD STM32F401xE ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex®-M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator allowing 0-wait state execution

Contextual Info: STM32F401xD STM32F401xE ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 512KB Flash/96KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator™ allowing 0-wait state execution

WLCSP49

Contextual Info: STM32F401xB STM32F401xC ARM Cortex-M4 32b MCU+FPU, 105 DMIPS, 256KB Flash/64KB RAM, 10 TIMs, 1 ADC, 11 comm. interfaces Datasheet - production data Features • Core: ARM 32-bit Cortex -M4 CPU with FPU, Adaptive real-time accelerator ART Accelerator™ allowing 0-wait state execution

E3000W

Abstract: hd6473332 HD-64 PC keyboard controller HD6473332f10
Contextual Info: Section 1 Overview The H8/3332 is a single-chip embedded controller with an H8/300 CPU core and a complement of on-chip supporting modules. They are particularly suited for keyboard control in notebook computers and similar applications. The H8/300 CPU is a high-speed processor with a Hitachi-original architecture featuring powerful

Contextual Info: 256KB/1MB/4MB IDT79R4000 SECONDARY CACHE MODULE BLOCK FAMILY PRELIMINARY IDT7MP6074 IDT7MP6084 IDT7MP6094 FEATURES: DESCRIPTION: • High-speed B iC E M O S /C E M O S ™ secondary cache module block constructed to support the IDT79R4000 CPU • Available as a pin compatible family to build 256 kilobyte

IDT79R4000

Contextual Info: 256KB/1MB/ 4MB IDT79R4000 SECONDARY CACHE MODULE BLOCK FAMILY PRELIMINARY IDT7MP6074 IDT7MP6084 IDT7MP6094 FEATURES: DESCRIPTION: • High-speed BiCMOS/CMOS secondary cache module block constructed to support the IDT79R4000 CPU • Available as a pin compatible family to build 256KB uni­

Contextual Info: * IDT79R3081-25MJ 1/3 IL00 C-MOS RISC CPU 1 GND VDD(+5V) 80 75 GND 5 VDD(+5V) 10 GND VDD(+5V) —TOP VIEW— GND VDD(+5V) 15 70 VDD(+5V) GND 20 GND VDD(+5V) 65 25 60 GND VDD(+5V) VDD(+5V) 35 PIN I/O No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18

HD6415108

Abstract: hd6415108f HD64151 AL P6O hd641510
Contextual Info: Section 1 Overview 1.1 Features The H8/510 is an original Hitachi CMOS microcomputer unit MCU comprising a highperformance CPU core with an internal 16-bit architecture plus a full range of supporting functions. The CPU features a highly orthogonal instruction set that permits addressing modes and data sizes