84 PIN CPU Search Results

Contextual Info: M32C/84 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER 1. Overview The M32C/84 is a single-chip microcomputer that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/84 group is available in 144-pin and 100-pin plastic molded

M30843MW-XXXGP

Contextual Info: M32C/84 Group SINGLE-CHIP 16/32-BIT CMOS MICROCOMPUTER REJ03B0047-0052Z Rev.0.52 Mar. 12, 2004 1. Overview The M32C/84 is a single-chip microcomputer that utilizes high-performance silicon gate CMOS technology with the M32C/80 series CPU core. The M32C/84 group is available in 144-pin and 100-pin plastic molded

BCRT-30

Abstract: 12MHZ 1553B UT1553B MIL-STD-1553B D1398
Contextual Info: UT1553B BCRT ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553B dual-redundant ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT mode ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

UT1553BCRTM

Abstract: 265u 11TA31 UT1553 UT1553B rta2
Contextual Info: UT1553 BCRTM ❐ DMA or pseudo-dual-port memory interface with FEATURES ❐ Comprehensive MIL-STD-1553 dual-redundant Bus ❐ ❐ ❐ ❐ 64K addressability ❐ Internal wraparound self-test ❐ Time tagging and message logging in RT and M modes ❐ Packaged in 84-pin pingrid array, 84-lead flatpack, or

P113

Abstract: P114 P115 Z87000 Z87010 Z87L00
Contextual Info: PRELIMINARY PRODUCT SPECIFICATION 1 Z87000/Z87L00 1 SPREAD SPECTRUM CONTROLLERS FEATURES Device ROM KWords RAM* I/O (Words) Lines Z87000 12 512 32 Z87L00 12 512 32 Package Information • 84-Pin PLCC 100-Pin QFP 100-Pin QFP Note: *General-Purpose ■ ■

P110

Abstract: P111 P112 P113 P114 P115 Z87000 Z87010 CP FSK modulator and Demodulator SPREAD-SPECTRUM SYSTEM
Contextual Info: PRELIMINARY PRODUCT SPECIFICATION 1 Z87000 1 SPREAD-SPECTRUM CONTROLLER FEATURES Device ROM KWords Z87000 12 RAM* I/O (Words) Lines 512 32 – Package Information 84-Pin PLCC 100-Pin QFP • Note: *General-Purpose ■ ■ User-Modifiable Features Software

PIC18CXXX

Abstract: ds39500 PIC18CXX8 microcontroller can PIC18CXXX family.data sheet DS00092 DS00167 PIC18C658 PIC18C858 PIC18CXX8 Microchip EPROM endurance
Contextual Info: PIC18CXX8 Microcontroller Family The 68-pin PIC18C658 and 84-pin PIC18C858 features the CAN Controller Area Network Rev. 2.0B Active serial communication interface. These devices are based on the powerful PIC18CXXX PICmicro MCU architecture and include an 8 x 8 single cycle

KB 7780

Abstract: MT90823AL sfe 5,5 ma sfe 5,5 mb MT90823 MT90823AB MT90823AG MT90823AP ST06 ST08
Contextual Info: MT90823 M ITEL 3V Large Digital Switch S E M IC O N D U C T O R DS5064 Features ISSUE 3 2,048 x 2,048 channel non-blocking sw itching at 8.192 Mb/s O rdering Inform ation MT90823AP 84 Pin PLCC MT90823AL 100 Pin MQFP MT90823AB 100 Pin LQFP MT90823AG 120 Pin PBGA

Cordless Phone system block diagram

Abstract: Transceiver Base Station TDD Cordless telephone system block diagram TDD synchronizer frequency hopping spread spectrum 900 Cordless Phone block diagram Z87000 Z87010 fsk modulator Transceiver TDD
Contextual Info: 1 Z87000 1 SPREAD-SPECTRUM CONTROLLER FEATURES Device ROM KWords Z87000 12 RAM* I/O (Words) Lines 512 32 – Package Information 84-Pin PLCC 100-Pin QFP • Note: *General-Purpose ■ ■ User-Modifiable Features Software Governs Phone Transceiver Circuitry Provides Primary Cordless Phone

p51 apple

Contextual Info: WDC THE WESTERN DESIGN CENTER, INC. W65C265S SECTION 2 PIN FUNCTION DESCRIPTION W65C265S Interface Requirements This section describes the interface requirements for the W65C265S single chip microcomputer. Figure 2-1 is the Interface Diagram for the W65C265S and Figure 2-2 shows the 84 Lead Chip Carrier pin out

EQUIVALENT TIMER IC WITH CD 4060

Abstract: 5q-5g 84 pin plcc ic base R3041
Contextual Info: IDT79R3041 IDT79RV3041 IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS Double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls

Contextual Info: IDT79R3041 IDT79RV3041 IDT79R3041 INTEGRATED RISController FOR LOW-COST SYSTEMS Double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls

Contextual Info: WD76C30ALV DESCRIPTION 1.0 DESCRIPTION 1.1 WD76C30ALV FEATURES • 84-pin PQFP package • Two fully programmable and independent serial I/O ports, configurable as PC/AT compatible WD16C452 or PS/2 compatible (WD16C552) o Loopback controls for communications link

Multibus ii protocol

Abstract: Multibus arbitration protocol 486 system bus
Contextual Info: TO SHIBA INTEGRATED CIRCUIT BAC TECHNICAL D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION ' The MULTIBUS II Bus Arbiter/Contro1ler (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

PIC18f452 frequency counter

Abstract: usart C18 CODE PIC18XXXX USART PIC applications PIC16XXXX DS30475 PIC18f452 timer0 codes PIC18F452 timer0 DS39026 ds39500
Contextual Info: PIC18XXXX Microcontroller Family Product Information The PIC18XXXX microcontroller family provides PICmicro devices in 8- to 84-pin packages, that are both socket and software upwardly compatible to the PIC16XXXX family. The PIC18XXXX family includes all the popular peripherals, such as MSSP, ESCI,

MIPS R3051

Contextual Info: Integrated Device Technology, Inc. Single, double-frequency clock input 16.67MHz, 20MHz, 25MHz and 33MHz operation 20MIPS at 25MHz Low cost 84-pin PLCC packaging On-chip 4-deep write buffer eliminates memory write stalls On-chip 4-word read buffer supports burst or simple block

Contextual Info: P r e l im in a r y P r o d u c t S p e c if ic a t/o n v % \ Z87000/Z87L00 S pread S pectrum C o n tr o ller s FEATURES Device ROM KWords RAM* (Words) I/O Lines Package Information Z87000 12 512 32 Z87L00 12 512 32 84-Pin PLCC 100-Pin QFP 100-Pin QFP Note: *General-Purpose

Contextual Info: AT43216 Features • One-Chip SCSI-2 Fast Architecture Controller for Host and 8-blt or 16-btt Peripheral Applications • 84-Pin PLCC Package, Sub-Micron CMOS Technology • Supports ANSI X3T9.2 SCSI Standard, with SCSI-2 Fast Architecture • Functions as an Initiator or a Target

Contextual Info: df) IDT79R3041 INTEGRATED RISController™ FOR LOW-COST SYSTEMS ADVANCE ,NFX ? S ïïi2 ï In te g ra te d Dev Ic e T ec hnology, In c . FEATURES: Single, double-frequency clock input 16 and 20MHz operation 14 MIPS at 20MHz Low cost 84-pin PLCC packaging

Multibus ii protocol

Abstract: Multibus arbitration protocol
Contextual Info: TOSHIBA INTEGRATED CIRCUIT BAC 8 4 1 1 0 TE C H N IC A L D A T A BAC Bus Arbiter/Controller GENERAL DESCRIPTION The MULTIBUS II Bus Arbiter/Controller (BAC) is an 84-pin, CMOS component that embodies the Arbitration and system control line functions of the MULTIBUS II

FE3020

Abstract: FE3030 FE3010 80286 interrupt table Motherboard IBM t21 faraday 80286 80286 microprocessor pin out diagram faraday fe3000 FE3000 Faraday Electronics
Contextual Info: IHfflMHIT^á ITI A i\ 7 IBS FE 3010 AT PERIPHERAL CONTROL LOGIC • ■ ■ ■ ■ 100% hardw are and software com patible to the IBM PC-AT 15 interrupt channels 3 tim er channels 7 DMA channels TTL-com patible ■ ■ ■ ■ ■ 84-pin, J-type leaded surface

UM83021

Abstract: 74LS629 8031 pin diagram ZA12 2A15 ST-506 UM83C022 ZA13 8031 driver Unicorn Microelectronics
Contextual Info: UNICORN MI CRO ELECTRONI CS H4E D TS7é7ññ OOQGMll 1 • :3 T -5 2 -23-62 UM83C022 AT HDC Interface PR ELIM INARY Features Buffer size 4k bytes Sector size 512 bytes 84-pin PLCC package ■ IBM PC/AT interface compatible ■ Jumper selectable for R LL/MFM disk interface

Contextual Info: Integrated Device Technology, Inc* Single, double-frequency clock input 16.67MHz, 20MHz, 25M Hz and 33MHz operation 16MIPS a t2 0M H z Low cost 84-pin PLCC packaging O n-chip 4-deep write buffer elim inates memory write stalls O n-chip 4-word read buffer supports burst o r sim ple block

uP1514

Abstract: R3721 IDT79R3721 IDT79R37
Contextual Info: DRAM CONTROLLER FOR THE R3051 FAMILY PRELIMINARY IDT79R3721 Integrated Device Technology, Inc. FEATURES • S upp orts all bus tra nsfers of the R3051 fam ily — P age m ode reads and w rites — Q uad w ord reads — N orm al read o r w rite accesses • 84-pin P LC C