8086 MICROCOMPUTER Search Results

Contextual Info: intei M8259A PROGRAMMABLE INTERRUPT CONTROLLER Military 8086, 8088, 80186 Compatible MCS -85 Compatible Eight-Level Priority Controller Expandable to 64 Levels Programmable Interrupt Modes Individual Request Mask Capability Single + 5V Supply No Clocks

8741A

Abstract: jnib NEC 8048 pd8741a 8086 with eprom pd82c43 upd8741 8080A 8085A JPD8041AHC
Contextual Info: mPD8041AH, mPD8741A NEC 8-BIT, SINGLE-CHIP NMOS MICROCOMPUTERS W ITH UNIVERSAL PPI NEC Electronics Inc. Pin Configuration Description The fiPD8041AH and jjPD8741A are programmable pe­ ripheral interface controllers intended for use in master/ slave configurations with 8048,8080A, 8085A, 8086, and

80188 8087

Abstract: intel 80186 instruction set 80186xl ARCHITECTURE OF 80186 PROCESSOR intel 80188 80188 programming peripheral 80186 reference manual 80186 intel 80186 external memory 80186 architecture
Contextual Info: 80186 80188 HIGH-INTEGRATION 16-BIT MICROPROCESSORS Y Integrated Feature Set Enhanced 8086-2 CPU Clock Generator 2 Independent DMA Channels Programmable Interrupt Controller 3 Programmable 16-bit Timers Programmable Memory and Peripheral Chip-Select Logic

reflectometer

Abstract: BIT1502
Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE IN DEVELOPMENT DISTINCTIVE CHARACTERISTICS GEN ERA L DESCRIPTION • Compatible with Ethernet specifications • Easily interfaced to 8086, 68000, Z8000, LSI-II microprocessors • On-board DMA and buffer management

AM7990

Contextual Info: Am7990 Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS • • • • • Compatible with Ethernet and IEEE-802.3 10Base5 Type A, and 10Base2 Type B, "C heapernet") Easily interfaced to 8086, 68000, Z8000*, LSI-II* microprocessors

Intel 8237 dma controller block diagram

Abstract: DMA interface 8237 WITH 8088 DMA Controller 8257 8086 8257 DMA controller intel d 8274 intel 8257 interrupt controller intel 8274 8257 intel block and pin diagram of 8257 dma 8257
Contextual Info: 8274 MULTI-PROTOCOL SERIAL CONTROLLER MPSC Asynchronous, Byte Synchronous and Bit Synchronous Operation Two Independent Full Duplex Transmitters and Receivers Fully Compatible with 8048, 8051, 8085, 8088, 8086, 80188 and 80186 CPU’s; 8257 and 8237 DMA Controllers; and

8086 8257 DMA controller

Abstract: Intel 8237 dma controller block diagram block and pin diagram of 8257 intel 8257 interrupt controller Block Diagram of 8237 DMA Controller 8257 CCITT-16 DMA interface 8237 WITH 8088 intel 8274 pin diagram of 8257
Contextual Info: intei 8274 MULTI-PROTOCOL SERIAL CONTROLLER MPSC Asynchronous, Byte Synchronous and Bit Synchronous Operation Two Independent Full Duplex Transmitters and Receivers Fully Compatible with 804B, 8051, 8085, 8088, 8086, 80188 and 80186 CPU's; 8257 and 8237 DMA Controllers; and

am8160

Abstract: str f 6167 Amz8127 74LS240 MC68000 Z8000 Z80A Z80B 50lh 71p3ns
Contextual Info: Am8163/Am8167 Am 8163/Am 8167 Dynamic Memory Timing, Refresh and EDC Controllers DISTINCTIVE CHARACTERISTICS EDC error flag latches for error logging under software control Two timing configurations support a broad range of processors Z80, Z8000, 8086, 8088, MC68000

Siemens 80186

Abstract: so do chan 4558 82257 SAB 80186 SAB82257 8086 a23 445-1 i82257
Contextual Info: Advanced DMA Controller SAB 82257 for 8-/16-Bit Microcomputer Systems 8 MHz • High-performance 16-bit DMA controller for 16-bit family processors SAB 80286, SAB 80186/188, SAB 8086/88 • 4 independent high-speed DMA channels • Adaptive on-chip bus interface for

Contextual Info: in te i 80C186EC/80C188EC AND 80L186EC/80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS • Fully Static Operation H True CMOS Inputs and Outputs ■ Integrated Feature Set: — Low-Power, Static, Enhanced 8086 CPU Core — Two Independent DMA Supported

8086 opcode sheet

Abstract: VL82C59A08QC command word of 8259 VL82C59A08PC APX88 MCS-80
Contextual Info: VLSI T ech n o lo g y , in c . VL82C59A PROGRAMMABLE INTERRUPT CONTROLLER FEATURES DESCRIPTION • Compatible with 8086, 8088, and similar microprocessors The VL82C59A Programmable Interrupt Controller can manage up to eight vectored priority interrupts for the

Contextual Info: It run REAL-TIME CLOCK JL RP/RF/RS5C62 OUTLINE The RP/ RF/ RS5C62 are CMOS LSIs which serve microcomputers as real-time clocks providing time, calendar, and alarm functions in direct coupling with the data buses of CPUs such as 8086 and 68000. A built-in timer counter

AM22V10

Abstract: MS 1117
Contextual Info: Am7990* Am7990* Local Area Network Controller for Ethernet LANCE DISTINCTIVE CHARACTERISTICS • • • • Ethernet and IEEE 802.3 compatible Easily interfaced to 8086, 68000, Z8000, LSI-II micro­ processors On-board DMA and buffer management, 48 byte FIFO

Burroughs Self-Scan

Abstract: 82c55al
Contextual Info: TUNDRA CA82C55A PROGRAMMABLE PERIPHERAL INTERFACE • Pin and functional compatibility with the industry standard 8255A • Supports 8086/8088 and 80186/188 m icroprocessors • Very high speed - 1 0 , 8 and 5 MHz zero wait state operation • Low power CMOS Implementation

interfacing 8259A to the 8086

Abstract: 80C187 80C186EC 80C186EC20 80C186EC25 80C188EC 80C188EC20 80C188EC25 80L186EC 80L188EC
Contextual Info: 80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud

80C186EC20

Abstract: intel 8086 instruction set 272332 GCS7 80c186ec
Contextual Info: 80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud

interfacing 8259A to the 8086

Abstract: 80C186EC 80C186EC20 80C186EC25 80C187 80C188EC 80C188EC20 80C188EC25 80L186EC 80L188EC
Contextual Info: 80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud

crt terminal interfacing in 8086

Contextual Info: NEWBRIDGE CA82C55A MICROSYSTEMS PROGRAMMABLE PERIPHERAL INTERFACE • Pin and functional compatibility with the industry standard 8255A • Supports 8086/8088 and 80186/188 microprocessors • Very high speed -1 0 ,8 and 5 MHz zero wait state operation • Low power CMOS Implementation

a23 445-1 409

Abstract: 82257 sab80186 siemens s7 IM 365 82257-N SAB 80186 SIEMENS et 200 cpu
Contextual Info: SIEM ENS Advanced DMA Controller SAB 82257 for 8-/16-Bit Microcomputer Systems Prelim inary • High-perform ance 16-bit DMA controller for 16-bit family processors SAB 80286, SAB 80186/188, SAB 8086/88 • 4 independent high-speed DMA channels • Adaptive on-chip bus interface for

Burroughs Self-Scan

Abstract: KD 2107 6 PIN
Contextual Info: TUNDRA CA82C55A PROGRAMMABLE PERIPHERAL INTERFACE • Pin and functional compatibility with the industry standard 8255A • Su pports 8086/8088 and 80186/188 microprocessors • Very high speed - 1 0 ,8 and 5 MHz zero wait state operation • Low power CMOS Implementation

MCS-85

Contextual Info: in iß l M8259A PROGRAMMABLE INTERRUPT CONTROLLER Military • ■ ■ ■ 8086, 8088, 80186 Compatible MCS -85 Compatible Eight-Level Priority Controller Expandable to 64 Levels ■ ■ ■ ■ Programmable Interrupt Modes Individual Request Mask Capability

Contextual Info: VL82C54 TK PRODUCT BRIEF PROGRAMMABLE INTERVAL TIMER FEATURES DESCRIPTION • Compatible 8080A, 8085A, 8086, 8088, and similiar microprocessors • Counts in binary or BCD • Clock inputs from dc to maximum clock operating frequency • Status may be read back on

182c55a

Abstract: 82C55A-2
Contextual Info: in te i 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE Compatible with all Intel and Most Other Microprocessors Control Word Read-Back Capability High Speed, “Zero Wait State” Operation with 8 MHz 8086/88 and 80186/188 2.5 mA DC Drive Capability on all I/O

01FF0

Abstract: b2c54
Contextual Info: in te i 82C54 CHMOS PROGRAMMABLE INTERVAL TIMER Three independent 16-bit counters Compatible with all Intel and most other microprocessors Low Power CHMOS — Ice = 10 mA @ 8 MHz Count frequency High Speed, “Zero Wait State” Operation with 8 MHz 8086/88 and