8005 TA 141 Search Results
8005 TA 141 Result Highlights (5)
Part | ECAD Model | Manufacturer | Description | Download | Buy |
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10106137-8005001LF |
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PwrBlade+® , Power Connectors, 4HP+20S+4HP PF, Vertical, Header. | |||
10131758-005RLF |
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PCIe M.2, Storage and Server Connector, H8.50mm, Key M, 0.76um (30.000u\\) Gold Plating, 0.50mm Pitch | |||
10106139-8005002LF |
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PwrBlade+® , Power Connectors, 4HP+20S+4HP PF, Vertical, Receptacle. | |||
G888005061THR |
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Board mount - Header Receptacle - Wire to Board 2.54mm Pitch Right Angle DIP,1x5Pin,Matte Tin,NY4T,Color-Black,Tray | |||
10080054-505LF |
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Quickie Header, Wire to Board Connector, Double Row, 26 Positions, Press-Fit Eject Latch Header 2.54 mm 0.76 um (30 u\\.) Gold or GXT™ Mating Plating. |
8005 TA 141 Datasheets Context Search
Catalog Datasheet | Type | Document Tags | |
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74LS45
Abstract: DRAM 4464 uses of 74ls245 to speed up buses tms 4464 10BASE-7 NQ8005 logic diagram of 74LS245 4464 dram ns-1a 0.1 ohm 1.0% 74LS245
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OCR Scan |
10BASE-5) 10BASE-2) 10BASE-7) MD400031/E 74LS45 DRAM 4464 uses of 74ls245 to speed up buses tms 4464 10BASE-7 NQ8005 logic diagram of 74LS245 4464 dram ns-1a 0.1 ohm 1.0% 74LS245 | |
Contextual Info: 8005 Advanced Ethernet Data Link Controller AEDLC June 1991 Features • Conforms to IEEE 802.3 Standard • Ethernet (10BASE-5) Cheapernet ( 10BASE-2) and Twisted Pair (10BASE-T) Flexible System Bus Interface • 8 or 16 Bit Data Transfers with Byte Swap |
OCR Scan |
10BASE-5) 10BASE-2) 10BASE-T) MD400031/E | |
Contextual Info: 8005 Advanced Ethernet Data Link Controller AEDLC June 1991 Features • Conforms to IEEE 802.3 Standard • Ethernet (10BASE-5) Cheapernet (10BASE-2) and Twisted Pair (10BASE-T) Flexible System Bus Interface • 8 or 16 Bit Data Transfers with Byte Swap |
OCR Scan |
10BASE-5) 10BASE-2) 10BASE-T) MD400031/E | |
74ls45
Abstract: SEEQ EDLC
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OCR Scan |
10BASE-S) 10BASE-2) 10BASE-T) 8005/80C04 MD400031/F 74ls45 SEEQ EDLC | |
Contextual Info: A P R 1 8 fl* 8005 Advanced Ethernet Data Link Controller March 1991 PRELIMINARY Features • Conforms to IEEE 802,3 Standard Ethernet 10BASES Chsepemet (10BASE2) and Twisted Pair (10BASE-T) ■ Flexible System Bus Interface • 8 or 16 Bit Data Transfers with Byte Swap |
OCR Scan |
10BASES) 10BASE2) 10BASE-T) MD400031/D | |
Contextual Info: EC Connectors The Anderson Pow er E C Connector Concept Anderson Power Products® EC connector is a steel housed connector that is used on battery operated equipment. Data Table Nominal Amperaae Votlage Rating Current Rating 300 250 300 amp on 4/0 AWG 16.38 mm cable |
OCR Scan |
F5840 5842X 5842G 5841X | |
1300G3
Abstract: M542G-A-889G/W
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OCR Scan |
110G10 110G11 110G12 110G15 110G16 110G17 110G18 110G19 110G20 110G21 1300G3 M542G-A-889G/W | |
mecm
Abstract: assembly instruction 9006 EPOC32 UCB1100 UCB1200 SA1100 SA-1100 StrongARM* SA-1100 Portable Communication Microcontroller 28-July-1995 partition look-aside table
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SA-1100 mecm assembly instruction 9006 EPOC32 UCB1100 UCB1200 SA1100 StrongARM* SA-1100 Portable Communication Microcontroller 28-July-1995 partition look-aside table | |
Contextual Info: Introduction 1.0 Introduction The DIGITAL Semiconductor SA-1100 Microprocessor SA-1100 is a general-purpose, 32-bit RISC microprocessor with a 16KB instruction cache, an 8KB write-back data cache, a minicache, a write buffer, a read buffer, and a memory-management unit (MMU) combined in a single chip. The SA-1100 is software compatible with the ARM V4 |
OCR Scan |
SA-1100 SA-1100) 32-bit SA-110 SA-110) 12-byte | |
LM 886 IC chip
Abstract: cA810
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OCR Scan |
10BASE5) IEEE802 10BASE2) SEEQ8003a LM 886 IC chip cA810 | |
Contextual Info: AutoDUPLEX CMOS Ethernet Data Link Controller Technology, Incorporated PRELIMINARY April 1993 Features • C onform s to IEEE 802.3 sta n d a rd fo r Ethernet 10BASES , C heapernet (10BASE2) a n d Twisted P air (10BASE-T). ■ High perform ance, lo w p o w e r CMOS technology. |
OCR Scan |
10BASES) 10BASE2) 10BASE-T) 80C04 80C04 8005/80C04 MD400120/A | |
F65535Contextual Info: 80C04A Technology, ,nOTPor.,.d A u to D U P L E X C M D a ta O L in k S E th e r n e t C PRELIMINARY o n t r o lle r March 1994 Features • Pinout and function compatible with the 80C04 except tor the function o f bits 3 through 6 o f the Transmit Packet Status Byte. |
OCR Scan |
80C04A 80C04 80C04A 8005/80C04 MD400120/D F65535 | |
F65535
Abstract: 74LS4S ST L 6203
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OCR Scan |
80C04A 80C04 30C04 F65535 74LS4S ST L 6203 | |
DRAM 4464
Abstract: 4464 dram tms 4464 74LS45 80C04A 226 35K 10BASE2 10BASE5 16-BYTE 74LS245
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80C04A 80C04 x3051. 80C04A 8005/80C04 MD400121/B DRAM 4464 4464 dram tms 4464 74LS45 226 35K 10BASE2 10BASE5 16-BYTE 74LS245 | |
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Contextual Info: SIEMENS 3.3V 8M x 64-Bit EDO-DRAM Module 3.3V 8M x 72-Bit EDO-DRAM Module HYM64V8005GU-50/-60 HYM64V8045GU-50/-60 HYM72V8005GU-50/-60 HYM72V8045GU-50/-60 168pin unbuffered DIMM Module with serial presence detect • 168 Pin JED EC Standard, U nbuffered 8 Byte Dual In-Line M em ory Module |
OCR Scan |
64-Bit 72-Bit HYM64V8005GU-50/-60 HYM64V8045GU-50/-60 HYM72V8005GU-50/-60 HYM72V8045GU-50/-60 168pin V8005/45GU-50/-60 | |
Contextual Info: LXT901A/907A Revision 1.0 Universal Ethernet Transceiver General Description Features The LXT901A and LXT907A Universal Ethernet Transceivers are new-generation LXT901 and LXT907 replacements with improved noise immunity and output filtering. The feature set of the LXT901A/907A has been |
OCR Scan |
LXT901A/907A LXT901A LXT907A LXT901 LXT907 LXT901A/907A 10BASE-T | |
HD-20
Abstract: HD-22 HDE-20 HDF-20 HDP-20 HDP-22
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OCR Scan |
HD-20 7S7312 2R74tl HD-22 HDE-20 HDF-20 HDP-20 HDP-22 | |
mx25l8005
Abstract: MX25L8005PC-15G MX25L8005M2C-15G mx25l800 mx25l8005m2c MX 15G MX25L8005M2I-15G 25L8005 05F0 8096 instruction
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MX25L8005 100mA 86MHz 66MHz 256-byte mx25l8005 MX25L8005PC-15G MX25L8005M2C-15G mx25l800 mx25l8005m2c MX 15G MX25L8005M2I-15G 25L8005 05F0 8096 instruction | |
MX25V8005Contextual Info: MX25V8005 8M-BIT [x 1] 2.5V CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface SPI compatible - Mode 0 and Mode 3 • 8,388,608 x 1 bit structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 16 Equal Blocks with 64K byte each |
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MX25V8005 100mA 50MHz 256-byte 120ms 64K-byte MX25V8005 | |
KH25L8005
Abstract: PM1307 KH25L
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KH25L8005 100mA 66MHz 256-byte 120ms KH25L8005 PM1307 KH25L | |
mx25l8005
Abstract: spi flash MX25L8005PC-15G MX25L8005M2I-12G
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MX25L8005 100mA 86MHz 66MHz 256-byte 120ms mx25l8005 spi flash MX25L8005PC-15G MX25L8005M2I-12G | |
Contextual Info: MX25L8005 8M-BIT [x 1] CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface SPI compatible - Mode 0 and Mode 3 • 8,388,608 x 1 bit structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 16 Equal Blocks with 64K byte each |
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MX25L8005 100mA 70MHz 66MHz 256-byte | |
opr 1139-3
Abstract: ia181 LED display 12 lines, 40 characters each, 10x8 SA1100 StrongARM* SA-1100 Portable Communication Microcontroller 28-July-1995 resistor de 27k ohm ppc jtag 115114 scr
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SA-1100 SA-1100 32-bit SA-110, opr 1139-3 ia181 LED display 12 lines, 40 characters each, 10x8 SA1100 StrongARM* SA-1100 Portable Communication Microcontroller 28-July-1995 resistor de 27k ohm ppc jtag 115114 scr | |
Contextual Info: MX25V8005 8M-BIT [x 1] 2.5V CMOS SERIAL FLASH FEATURES GENERAL • Serial Peripheral Interface SPI compatible - Mode 0 and Mode 3 • 8,388,608 x 1 bit structure • 256 Equal Sectors with 4K byte each - Any Sector can be erased individually • 16 Equal Blocks with 64K byte each |
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MX25V8005 100mA 50MHz 256-byte 120ms |