8 PIN DIP J K FLIPFLOP IC Search Results

TEA1007

Abstract: 1007 ignition triac control circuit diagram telefunken 1007 vinax
Contextual Info: Tem ic TEA1007 S e m i c o n d u c t o r s Simple Phase-Control Circuit Description The integrated circuit TEA 1007 is designed as a general phase-control circuit in bipolar technology. It has an internal supply voltage limitation. With typical 150 mA ignition pulse, it is possible to determine the phase shift

LM6462

Abstract: LF411 "direct replacement" LH0032ACG LM6464 LM646 VARIABLE POWER SUPPLY. 0 - 30V, LM723 LM35,3 sensor vhdl 4-bit binary calculator ADC1231 lm2940-8
Contextual Info: N Military/Aerospace Division Product Line Card 1997 N www.national.com/appinfo/milaero/ Table of Contents At National Semiconductor , it’s about innovation. One of the largest suppliers of IC products for high reliability applications, we’ve provided analog and mixedsignal engineering for the Military/Aerospace market for more than 30 years. Our expertise in system design and

M74HC112

Abstract: M74HC112B1R M74HC112M1R M74HC112RM13TR M74HC112TTR PO13H TSSOP16
Contextual Info: M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

PO13H

Abstract: TSSOP16 M74HC112 M74HC112B1R M74HC112M1R M74HC112RM13TR M74HC112TTR
Contextual Info: M74HC112 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE:

M74HC113

Abstract: M74HC113B1R M74HC113M1R M74HC113RM13TR M74HC113TTR TSSOP14 8 pin dip j k flipflop ic
Contextual Info: M74HC113 DUAL J-K FLIP FLOP WITH PRESET • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 79MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

ui*321

Contextual Info: S E M IC O N D U C T O R 74F174 Hex D Flip-Flop w ith M aster Reset General Description Features The ’F174 is a high-speed hex D flip-flop. The device is used primarily as a 6-bit edge-triggered storage register. The infor­ mation on the D inputs is transferred to storage during the

M74HC107

Abstract: M74HC107B1R M74HC107M1R M74HC107RM13TR M74HC107TTR TSSOP14
Contextual Info: M74HC107 DUAL J-K FLIP FLOP WITH CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 80MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

74ALS

Abstract: 74ALS109A 74ALS109AD 74ALS109AN SC00042
Contextual Info: INTEGRATED CIRCUITS 74ALS109A Dual J-K positive edge-triggered flip-flop with set and reset Product specification IC05 Data Handbook Philips Semiconductors 1991 Feb 08 Philips Semiconductors Product specification Dual J-K positive edge triggered flip-flop

M74HC107

Abstract: M74HC107B1R M74HC107M1R M74HC107RM13TR M74HC107TTR TSSOP14
Contextual Info: M74HC107 DUAL J-K FLIP FLOP WITH CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 80MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

M74HC76

Abstract: M74HC76B1R M74HC76M1R M74HC76RM13TR M74HC76TTR PO13H TSSOP16 C2MOS
Contextual Info: M74HC76 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 67MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

M74HC73

Abstract: M74HC73B1R M74HC73M1R M74HC73RM13TR M74HC73TTR TSSOP14
Contextual Info: M74HC73 DUAL J-K FLIP FLOP WITH PRESET AND CLEAR • ■ ■ ■ ■ ■ ■ HIGH SPEED : fMAX = 80MHz TYP. at VCC = 6V LOW POWER DISSIPATION: ICC =2µA(MAX.) at TA=25°C HIGH NOISE IMMUNITY: VNIH = V NIL = 28 % VCC (MIN.) SYMMETRICAL OUTPUT IMPEDANCE: |IOH| = IOL = 4mA (MIN)

Contextual Info: E M IC O N D U C T O R T 74F114 Dual JK Negative Edge-Triggered Flip-Flop with Common Clocks and Clears General Description A synchronous Inputs: The ’F114 contains tw o high-speed JK flip-flops with com ­ mon C lock and C lear inputs. Synchronous state changes are

Contextual Info: S E M IC O N D U C T O R 74VHCT374A Octal D-Type Flip-Flop with 3-STATE Outputs General Description Features The VHCT374A is an advanced high speed CMOS octal flip-flop with 3-STATE output fabricated with silicon gate CMOS technology. It achieves the high speed operation

IC of XOR GATE

Abstract: "XOR Gate" PAL22R
Contextual Info: High Speed Programmable Array Logic PAL22RX8A Features/ Benefits Ordering Inform ation • Programmable flip-flops allow J-K, S-R, T or D-types lor the m oit efficient use of product terms PAL22RX8A C NS STD • 8 Input/output macrocells for flexibility PROGRAMMABLE

Contextual Info: Preliminary Commercial PEEL 18LV8Z-25 CMOS Programmable Electrically Erasable Logic Device FEATURES • Low Voltage, Ultra Low Power Operation - Vcc = 2.7 to 3.6 V - Icc =25 uA typical at standby - Icc = 2 mA (typical) at 1 MHz - Meets JEDEC LV Interface Spec (JESD8-A)

D flip-flop to T Flipflop circuit converter

Contextual Info: TECHNICAL DATA IN74HCT163A Presettable Counters High-Performance Silicon-Gate CMOS The IN74HCT163A is identical in pinout to the LS/ALS163. The IN74HCT163 may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs. The IN74HCT163A is programmable 4-bit synchronous counter that

Contextual Info: ADV MICRO PL A/ P L E / A R R AY S lt. Ï e | Q2S7S3t OÜSTOk"! Asynchronous PALI 6RA8 Ordering Information Features/Benefits • Programmable dock for asynchronous operation PAL16RA8 C N STD • Programmable asynchronous set and reset • Programmable polarity

Contextual Info: 74A C / A C T 11534 S ig n e t ic s Octal D-Type Flip-Flop; Positive-Edge Trigger 3-State , INV ACL Products Product Specification GENERAL INFORMATION FEATURES C O N D IT IO N S T . = 25°C ; G N D = 0V; VCC = 5.0V • 3-State output buffers • Common 3-State Output Enable

"J-K Flip flop"

Contextual Info: TECHNICAL DATA IN74HCT109A Dual J-K Flip-Flop with set and Reset High-Performance Silicon-Gate CMOS The IN74HCT109A is identical in pinout to the LS/ALS109. The IN74HCT109A may be used as a level converter for interfacing TTL or NMOS outputs to High Speed CMOS inputs.

PAL16RA8CN

Abstract: 6RA8
Contextual Info: Asynchronous PALI 6RA8 Ordering Information Features/ Benefits • Programmable clock for asynchronous operation « Programmable asynchronous set and reset PAL16RA8 C N STD • Programmable polarity • Programmable flip-flop bypass • Local and global output enable control

Contextual Info: Lattice GAL20RA10 High-Speed Asynchronous E2CM O S PLD Generic Array Logic F U N C T IO N A L B L O C K D IA G R A M FEATURES • HIGH PERFORM ANCE E*CM O S* TECHNOLOGY — 12 ns Maximum Propagation Delay — Fmax -71.4 MHz — 12 ns Maximum from Clock Input to Data Output

74ls112 pin diagram

Abstract: 74ls112 pin configuration 74LS112 N74S112D 74ls112 function table
Contextual Info: 7 4 LS1 1 2 , S 1 1 2 Flip-Flops S ig n e t ic s Dual J-K Edge-Triggered Flip-Flop Product Specification Logic Products DESCRIPTION The '112 is a dual J-K negative edgetriggered flip-flop featuring individual J, K, Clock, Set and_Reset inputs. The Set So and Reset (R d) inputs, when LOW,

KK74HC163A

Abstract: KK74HC163AD KK74HC163AN
Contextual Info: TECHNICAL DATA KK74HC163A Presettable Counters High-Performance Silicon-Gate CMOS The KK74HC163A is identical in pinout to the LS/ALS163. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.

KK74HC161A

Abstract: KK74HC161AD KK74HC161AN
Contextual Info: TECHNICAL DATA KK74HC161A Presettable Counters High-Performance Silicon-Gate CMOS The KK74HC161A is identical in pinout to the LS/ALS161. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LS/ALSTTL outputs.