77251 Search Results

TMP320F240PQ

Abstract: TMS320F240PQ SPRS066 F240 TMS320F240 SPRU160B TMX320F240PQ tmp320f240 132PQFP
Contextual Info: TMS320F240PQ ERRATA DSP CONTROLLER 132ĆPQFP SPRS066 APRIL 1998 ERRATA for TMS320F240PQ DSP Controller 132-PQFP Silicon Releases 1.1, 2.0, and 3.1 Copyright  1998, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 TMS320F240PQ ERRATA

TMS320F240

Abstract: instruction set of TMS320c24x DSP PROCESSOR TMP320F240PQ C240 F240 TMS320F240PQ txwake
Contextual Info: SPRS066A APRIL 1998 – REVISED JULY 1998 ’F240 DSP CONTROLLER ENHANCEMENTS and EXCEPTIONS for the ’F240 DSP Controller Silicon Releases 1.1, 2.0, 3.1, and 3.2 Copyright  1998, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443

SPRU282

Abstract: PQFP TMS320F texas instrument F243 SPRU160C F241 TMS320F241 TMS320F243 TMS320F20x
Contextual Info: SPRZ150 SEPTEMBER 1999 ’F243/’F241 DSP CONTROLLERS SILICON UPDATES for the TMS320F243 and TMS320F241 DSP Controllers Silicon Release 2.1 Copyright  1999, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SPRZ150 SEPTEMBER 1999

identification trace code texas

Abstract: SPRU210 TMS320VC5402 SPRZ155 TMS320VC5402 bootloading TMS320C5000 TMS320UC5402 TMS320VC5402PGE tms320 54x mcbsp SPRU173
Contextual Info: SPRZ155A NOVEMBER 1999 – REVISED JANUARY 2000 TMS320VC5402/TMS320UC5402 DSP SILICON UPDATES for the TMS320VC5402/TMS320UC5402 DSP Copyright  2000, Texas Instruments Incorporated POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 1 SPRZ155A NOVEMBER 1999 – REVISED JANUARY 2000

tr8c

Abstract: TMS28F200
Contextual Info: TMS28F20ÛBZT, TMS28F200BZB 262144 BY 8-BIT/131072 BY 16-BIT BOOT-BLOCK FLASH MEMORIES SWS2dOO - JUNE 1 9 9 4 - REVISED SEPTEMBER 1997 • ■ I I I • • • • • • • • • • Organization . . . 262144 by 8 bits 131072 by 16 bits Array-Blocking Architecture

NCC equivalent

Contextual Info: TMS29F400T, TMS29F400B 524288 BY 8-BIT/262144 BY 16-BIT FLASH M EMORIES • I • Single Power Supply Supports 5 V ± 10% Read/Write Operation I I • Organization . . . I • Array-Blocking Architecture - One 16K-Byte/One 8K-Word Boot Sector - Two 8K-Byte/4K-Word Parameter Sectors

27C020-12

Abstract: 27PC020-12 LS020 A1025 LS020B 2097152-BIT
Contextual Info: TMS27C020 2097152-BIT UV ERASABLE PROGRAMMABLE TMS27PC020 2097152-BIT PROGRAMMABLE READ-ONLY MEMORY SM LS020B - N O V E M B E R 1990 - REVISED JU N E 1995 • Organization . . . 256K x 8 J PACKAGE TOP VIEW • Single 5-V Power Supply • Operationally Compatible With Existing

Contextual Info: SMJ416160, SMJ418160 1048576-WORD BY 16-BIT HIGH-SPEED DRAM 1 SGMS720A - APRIL 1995 - REVISED JUNE 1995 XXX PACKAGE TOP VIEW ACCESS ACCESS ACCESS TIME TIME TIME '41x160-60 41x160-70 '41x160-80 • • • • • • • • tRAC MAX 60 ns 70 ns SO n* *CAC

TM4SN64EPN10

Abstract: TM2SN64EPN-10 TM48N64EPN TM4SN64EPN-10 TMS626812
Contextual Info: TM2SN64EPN 2097152 BY 64-BIT TM4SN64EPN 4194304 BY 64-BIT SYNCHRONOUS DYNAMIC RAM MODULES _ SYNCHRONOUS CLOCK CYCLE TIME *CK3 , {CL = 3 t ACCESS TIME CLOCK TO OUTPUT >CK2 CL = 2) *CK3 (CL = 3) *CK2 (CL = 2) • • • • • • • •

44c256

Abstract: 3034C
Contextual Info: SMJ44C256 262144 BY 4-BIT DYNAMIC RANDOM-ACCESS MEMORY _ SGMS034C - MAY 1989 - B E V ILO JUNE 1965 Organization. . . 262144 Words x 4 Bits Single 5-V Supply 10% Tolerance Processed to MIL-STD-833, Class B Performance Ranges: 3-State Unlatched Output

cd018

Contextual Info: TMS28F033 4194304-BIT SYNCHRONOUS FLASH MEMORY _ SM JS633 - NOVEMBER 1997 PAF 80-PIN PACKAGE TOP VIEW 8 X to. > i> 5 ¡r lo o Ear IS IS IS |w lo I * 0017 C D018 C DQ19 C VDDE C VSSE C OQ20 C 0Q21 C 0Q22 C DQ23 C DQ24 C DQ25 C

s29f

Contextual Info: TMS29F040 4194304-BIT FLASH MEMORY S M J S 8 2 0 A - A P R IL 1 9 9 6 - R E V IS E D J A N U A R Y 1 9 9 7 I * Single Power Supply 5 V ± 10% FM PACKAGE T O P V IE W cm lo co co O r~. < < < < > I5 < i— i l — i l — il— i l — i l — il— i 4 '

Contextual Info: TM4EP72BPB, TM4EP72BJB, 4194304 BY 72-BIT TM4EP72CPB, TM4EP72CJB 4194304 BY 72-BIT EXTENDED-DATA-OUT BUFFERED DYNAMIC RAM MODULES _ _ • • • • Long Refresh Periods: - TM4EP72CxB: 64 ms 4096 Cycles

TMS4C2970

Abstract: 4C2973-24 TMS4C2971 Bit Field Memory
Contextual Info: TMS4C2973 245760 BY 12-BIT FIELD MEMORY SMGS672 - OCTOBER 1997 • 2949120 Bits of Memory • Organization: 245760 Words x 12 Bits • Single 3.3-V Power Supply ± 10% Tolerance • Upwardly and Pin-to-Pin Compatible With TMS4C2970 and TMS4C2971 • 2-Port Memory With FIFO Operation

27A6

Contextual Info: TMS28F210 1048576-BIT FLASH MEMORY I SMJS210B - DECEMBER 1892 - REVISED JUNE 1995 N PACKAGE TOP VIE W Pin Compatible With Existing 1-Megabit EPROMs All Inputs/Outputs TTL Compatible Vcc Tolerance ±10% Maximum Access/Minimum Cycle Time ’28F210-10 100 ns

Contextual Info: SMJ684002 512K BY 84HT STATIC RANDOM-ACCESS MEMORY _ * Single 5-V ± 10% Power Supply HJA/HKE PACKAGE TOP ViEW f • • Fast Access Time 20125/35 ns Equal Address and Chip-Enable Access Time • • • All Inputs and Outputs Are TTL-Compatible

042b

Contextual Info: 74AC11138 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCAS042B - MAY 1988 - REVISED A P R IL I 996 D, N, OR PW PACKAGE TOP VIEW Designed Specifically for High-Speed Memory Decoders and Data Transmission Systems Y1 [ 1 Y2 [ 2 Incorporates Three Enable Inputs to

Contextual Info: TMS418160A 1048576 BY 16-BIT DYNAMIC RANDOM-ACCESS MEMORY S M K S 891C - A U G U S T 1996 - R EVISED O C TO BE R 1997 This data sheet is applicable to TMS418160As symbolized by Revision “E” and subsequent revisions as described in the device symbolization section.

tms jl 27C256-15

Abstract: tms jl 27c256-12 tms jl 27C256-10 TMS JL 27C256-20 TMS JE 27C256-15
Contextual Info: TMS27C256 32768 BY 8-BIT UV ERASABLE TMS27PC256 32768 BY 8-BIT PROGRAMMABLE READ-ONLY MEMORIES _ SMLS25BH- SEPTEMBER 1964 - REVISED NOVEMSER 1997 Organization . . . 32768 by 8 Bits J PACKAGE TO P VIEW Single 5-V Power Supply Pin Compatible With Existing 256K MOS

27c040-12

Contextual Info: SMJ27C040 524288 BY 8-BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY SGMS046B - NOVEMBER 1992 - REVISED SEPTEMBER 1997 Organization . . . 524288 by 8 Bits Single 5-V Power Supply Industry Standard 32-Pin Dual-In-line Package All Inputs/Outputs Fully TTL Compatible

5C100B-25

Abstract: 5C1008-25 20D14 5C100B
Contextual Info: SMJ5C1008 128K BY 8-BIT STATIC RANDOM-ACCESS MEMORY _ SQMS734A - MAY 1996 - REVISED JUNE 1997 Processed to MIL-PRF-38535 Organization . . . 128K Words x 8 Bits Fast Static Operation Single 5-V Supply ±10% Tolerance Maximum Access Time From Address or

SPW 12w

Abstract: TMS380c16 RRU 32
Contextual Info: TMS380C26 NETWORK COMMPROCESSOR SPW S010A -APRIL 1992- R E V IS E D MARCH 1993 I • IEEE 802.5 and IBM Token-Ring Network Compatible • Low-Cost Host-Slave I/O Interface Option • IEEE 802.3 and Blue Book Ethernet™ Network Compatible • Selectable Host System-Bus Options

SMOS182

Contextual Info: TMS626802, TMS636802 1048576-WORD BY 8-BIT BY 2-BANK SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES SMOS182 - FEBRUARY 1994 TM S626802 LVTTL DGE PACKAGE (TO P VIE W ) 3.3-V Power Supply (10% Tolerance) Two Banks for On-Chip Interleaving (Gapless Accesses) vcc [ 1

Contextual Info: SMJ44C251B 262144 BY 4-BIT MULTIPORT VIDEO RAM SGMS058A- MARCH 1995 - REVISED JUNE 19BS Military Operating Temperature Range -55 °C to 125°C Performance Ranges: AC CESS AC CESS ACCESS ACCESS TIME TIME TIME TIME ROW COLUM N SER IAL SER IAL ADDRESS EN ABLE