74LS20 IC Search Results

TTL 7421

Abstract: 7421 ttl AND gate 7421 pin configuration PIN CONFIGURATION 7420 TTL 7420 logic gate 7421 AND 74LS20 PIN CONFIGURATION 7420 pin configuration 7420 SIGNETICS TTL 74LS20
Contextual Info: 7420, 7421, LS20, LS21, S20 Signetics Gates Dual Four-Input NAND 20 AND (’21) Gate Product Specification Logic Products TYPE TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3 ns 8mA 7421 12ns 8mA 74LS21 9ns

ic 7421

Abstract: TTL 7421 7421 ttl AND gate IC 7420 pin configuration ic 7421 function ic 7421 TTL 7420 7421 IC ic ttl 7421 pin configuration ic 7420
Contextual Info: Signetics I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification H TYPICAL SUPPLY CURRENT (TOTAL) TYPICAL PROPAGATION DELAY TYPE 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21

7421 pin configuration

Abstract: 7420 pin configuration 74LS20 PIN CONFIGURATION 7421 logic gate 7421 AND 74LS20 function table 74LS21 PIN CONFIGURATION TTL 7420 7421 AND gate PIN CONFIGURATION 7420
Contextual Info: Signehcs I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 8mA 74S20 3ns 7421 12ns 8mA 74LS21

TTL 7421

Abstract: 7421 ttl AND gate TTL 7420 74LS21 PIN CONFIGURATION 7421 pin configuration 7420 pin configuration 74LS gates 7420 nand 74ls gate symbols PIN CONFIGURATION 7420
Contextual Info: Signetics I 7420, 7421, LS20, LS21, S20 Gates Logic Products Dual Four-Input NAND '20 AND ('21) Gate Product Specification • TYPICAL PROPAGATION DELAY TYPE TYPICAL SUPPLY CURRENT (TOTAL) 7420 10ns 8mA 74LS20 10ns 0.8mA 74S20 3ns 8mA 7421 12ns 8mA 74LS21

Contextual Info: LS TTL DN74LS Series DN74LS20 DN74LS20 Dual 4 - input P ositive NAND Gates H Description P-1 D N 74LS20 contains tw o 4-input positive isolation NAND gate circuits. • Features • • • • Low pow er consum ption P j = 4mW typical High speed ( t pd = 10ns typical)

Contextual Info: GD54/74LS20 DUAL 4-INPUT POSITIVE NAND GATES Description This device contains two independent 4-input NAND gates. It performs the Boolean functions y = A B-C D or Y = A + B + C + D in positive logic. Function Table each gate INPUTS OUTPUT N* V L L H H L

74LS20

Abstract: 751A-02 TTL 74ls20
Contextual Info: fQ MOTOROLA SN54/74LS20 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE Vcc jïïi LOW POWER SCHOTTKY [ïïi nu im ra m m J SUFFIX CERAMIC CASE 632-08 GND N SUFFIX p l a s t ic 14 I I I M ' 1 ,^ ^ 4 , CASE 646-0 D SUFFIX SOIC CASE 751A ORDERING INFORMATION

74LS20

Abstract: IC 7420 74LS20 fanout 74LS20pc pinout 7420 7420 ic 7420PC
Contextual Info: NATIONAL SEHICOND {LOGIC} DEE D | b S G H E 2 DOb3bSS ^ □ | 20 Y i-fS ' CO NNECTIO N DIAGRAMS PINOUT A 54/7420 54H/74H20 54S/74S20 54LS/74LS20 DUAL 4-INPUT NAND GATE ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE V cc = +5.0 V ±5%,

Contextual Info: lEE D I 7cH 7 G7 b 0QDEb3D P. | SANYO SEMICONDUCTOR CORP ¿C74HC20 3003A CMOS High-Speed Standard Logic LC74HC Series Dual 4-Input NÂND Gate Features • The LC74HC20 consists of 2 identical 4-input NAND gates. • Uses CMOS silicon gate process technology to achieve operating speeds similar to LS.TTL 74LS20 gates with the

74LS20

Abstract: TTL 74LS20 751A-02 truth table NOT gate 74
Contextual Info: SN54/74LS20 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

4 inputs OR gate truth table

Abstract: 74LS20 TTL 74ls20 truth table NAND gate 74 74Ls20 truth table 751A-02 4 inputs OR gate datasheet truth table NOT gate 74 74LS20 2 input SN74LSXXN
Contextual Info: SN54/74LS20 DUAL 4-INPUT NAND GATE DUAL 4-INPUT NAND GATE VCC 14 1 LOW POWER SCHOTTKY 13 2 12 11 3 4 10 5 9 6 8 J SUFFIX CERAMIC CASE 632-08 7 14 GND 1 N SUFFIX PLASTIC CASE 646-06 14 1 14 1 D SUFFIX SOIC CASE 751A-02 ORDERING INFORMATION SN54LSXXJ SN74LSXXN

N7420N

Abstract: N74S20N S54LS20 40011 74LS20 N7420F N74H20F N74H20N N74LS20N N74S20F
Contextual Info: PIN CONFIGURATIONS 54/7420 54H/74H20 54S/74S20 54LS/74LS20 ORDERING CODE {See Section 9 for further Package and Ordering Information. C O M M E R C IA L RANGES = 5V ± 5%; T a = 0°C to *70“ C PACKAGES PIN CO N F. P lastic DIP Fig. A Fig. A N7420N N74S20N

EN3911

Contextual Info: SANYO S E M I C O N D U CT O R CORP b3E D • 7TT7a7b GQ11177 HTS * T S A J Ordering number:EN3911_ I MLC74HC20M CMOS High-Speed Standard Logic Dual 4-Input NAND Gate F e a tu re s • The MLC74HC20M consists of 2 identical 4-input NAND gates. • Uses CMOS silicon gate process technology to achieve operating speeds sim ilar to LS ■TTL 74LS20

74Ls20 truth table

Contextual Info: g M O TO ROLA SN54/74LS20 vcc jü i r a r a rm r a it i m DUAL 4-INPUT NAND GATE ÜJ LÌJ LiJ Lll Ll I LiJ LzJ LO W P O W E R S C H O T T K Y J Suffix — Case 632-08 (Ceramic) N Suffix — Case 646-06 (Plastic} GUARANTEED OPERATING RANGES S YM B O L PARAMETER

IC 7420

Abstract: jrc 5011 74 HCL 4 TTL 7410 als 004 74LS20 7420 ic IC 7410 S20 rca TTL 7420
Contextual Info: - 34 - Dual 4 Input NAND 7420 o Y - Xh J0B y 'v 'l' N LS ALS ALSK F S AS AC tpd «ax L-*H t 22 15 U 8 6 4 .5 5 11. 1 12.3 23 35 tpd max H -L 1 15 15 10 7 5 .3 5 4 .5 11. 1 12. 3 23 35 ns Icc •ax High H 4 0 .8 0 .4 0 .8 1 .4 8 1 .6 0. 04 0. 04 0. 02 0 .0 2

UM82C11

Abstract: 82C11 cga video 6845 CRTC 6845 74ls20 pin diagram UM6845R cga video UM6845 82C11C logic diagram of 74LS245
Contextual Info: UNICORN MICROE LE CTRON ICS SHE D TS7fl7flö GGQ02SS t. • i s ^ ^ 5 .,. j a ^ s a UM 487 HCGA CONTROLLER PRELIM INARY Features ■ ■ ■ ■ ■ MGA Hercules and CGA compatible ■ Built-in 6845 CRTC ■ 64 K Bytes o f video memory Flicker-Free operation during CPU read/write

7404 TTL CMOS

Abstract: TTL 7400 fairchild TTL 74h04 7404 ttl inverter TTL 7404 fairchild 9016 CI 74LS00 TTL 7404 fairchild 74H00 TTL TTL 9016 fairchild TTL 7401
Contextual Info: FAIRCHILD LOGIC/CONNECTION DIAGRAMS DIGITAL-TTL D1 9016, 9S04, 54/7404, 54H/74H04, 54S/74S04, 54LS/74LS04, 9017, 9S05A, 54/7405, 54H/74H05, 54S/74S05, 54L8/74LS05, 54/7406, 54/7414, 54LS/74LS14, 54/7416 D2 9002, 54/7400, 54H/74H00, 54S/74S00, 54LS/74LS00, 9012,

Contextual Info: SCS-THOMSON lÄ g«LiM (s «S M54HC20 M74HC20 DUAL 4-INPUT NAND GATE • HIGH SPEED tpo = 8 ns (TYP.) AT Vcc = 5 V ■ LOW POWER DISSIPATION Ice = 1 nA (MAX.) AT Ta = 25 *C ■ HIGHNOISE IMMUNITY V nih = V n il = 28 % V c c (MIN.) ■ OUTPUT DRIVE CAPABILITY

74HC20 truth table

Abstract: 74HC20 equivalent LC109 74ls20 14 PIN 74HC20
Contextual Info: r z 7 SG S-T H O M SO N M54HC20 ^ 7 # M ^ ( » [ i û T O C S _ M74HC20 DUAL 4-INPUT NAND GATE • HIGH SPEED tpD = 8 ns (TYP. AT Vcc = 5 V ■ LOW POWER DISSIPATION Icc = 1 JiA (MAX.) AT T a = 25 ’C . HIGH NOISE IMMUNITY V n ih = V nil = 28 % V c c (MIN.)

Contextual Info: M54HC20 M74HC20 SGS-THOMSON G l DUAL 4-INPUT NAND GATE HIGH SPEED tPD = 10 ns TYP. at VCc = 5V LOW POWER DISSIPATION ICC = 1 *A (MAX.) at T a = 2 5 °C HIGH NOISE IM M U N ITY V NIH = V NIL = 2 8 % V q c (MIN.) O U TPU T DRIVE CAPABILITY 10 LSTTL LOADS

74LS20 ic

Abstract: M54HC20 M54HC20F1R M74HC20 M74HC20B1R M74HC20C1R M74HC20M1R 74Ls20 truth table
Contextual Info: M54HC20 M74HC20 DUAL 4-INPUT NAND GATE . . . . . . . . HIGH SPEED tPD = 8 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

74LS20 ic

Abstract: M74HC20 M74HC20B1R M74HC20C1R M74HC20M1R M54HC20 M54HC20F1R
Contextual Info: M54HC20 M74HC20 DUAL 4-INPUT NAND GATE . . . . . . . . HIGH SPEED tPD = 8 ns TYP. AT VCC = 5 V LOW POWER DISSIPATION ICC = 1 µA (MAX.) AT TA = 25 °C HIGH NOISE IMMUNITY VNIH = VNIL = 28 % VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE

Contextual Info: TC74HC20AP/AF/AFN DUAL 4-INPUT NAND GATE T h e TC 74H C 20A is a h igh speed C M O S 4 - I N P U T NAND G A TE fa b r ic a te d w ith silico n g a te C 'M O S tech n ology . It ach ie v e s the high speed o p e ratio n s i m i l a r to e q u iv a len t L S T T L w hile m a in ta in in g the C M O S low pow er

74HC20

Contextual Info: M54HC20 M74HC20 SGS-TffOMSON li gTFl@iQ(gi DUAL 4-INPUT NAND GATE HIGH SPEED tpo = 10 ns (TYP. at V c c = 5V LOW POWER DISSIPATION lcc = 1pA (MAX.) at Ta = 25°C HIGH NOISE IMMUNITY V nih = V nil = 280/0 VCC (MIN.) OUTPUT DRIVE CAPABILITY 10 LSTTL LOADS SYMMETRICAL OUTPUT IMPEDANCE