74LS 04 N Search Results

Contextual Info: LS T T L D N 74LS Series DN74LS04 D N 74L S 04 Dio74-LS 04 Hex Inverters P-1 • Description D N 7 4 L S 0 4 c o n ta in s six in v e rte r c irc u its. ■ Features • • L ow p o w e r c o n su m p tio n P d = 12m W ty p ic a l H igh sp ee d ( t pd = 9 .5 n s ty p ic a l)

74163 four bit binary counter

Abstract: LS162A 74163 pin configuration counter diagram 74161 162 bcd 74160 function table pin diagram of 74163 pin diagram of 74160 74LS163A equivalent LS160A
Contextual Info: 74160, 74161, 74163, LS160A, LS161A, LS162A, LS163A S ig n e tic s Counters '160, '162 BCD Decade Counter '161, '163 4-Bit Binary Counter Logic Products Product Specification FEATURES • Synchronous counting and loading • Two Count Enable Inputs for nbit cascading

74170PC

Abstract: oc75 54170DM 54170FM 54LS170DM 74170DC 74170FC 74LS170DC 74LS170FC 74LS170PC
Contextual Info: / — 7 Q - u / ~ u / _ CO NNECTIO N DIAGRAM PINOUT A 54/74170 54LS /74LS 170 4 X 4 REGISTER FILE Dz [T 16] V cc □3 [2 T |]D i W ith O p e n -C o lle c to r O utputs D 4 [I u ] W Ao [7 Ï5 ] W Ai RAi 12] WE RAo |T DESCRIPTION — T he ’170 contains 16 high speed, low power, transparent

ic 74198

Abstract: sn 74198 74198
Contextual Info: LOGIC SYMBOL 54/74198 3 DESCRIPTION FEATURES The “ 198” is a 8 -Bit B idirectio nal Universal Shift R egiste r useful in a w ide varie ty of a p ­ plications. As a high speed m ultifunctional sequential building block, it may be used in seria l-seria l, s eria l-pa rallel, pa rallel-se rial,

74LS04 fan-out

Abstract: 7404PC 74LS04 pinout ls 7404 74LS04PC pin diagram of 7404 74ls04 hex inverter 74LS04P 74LS04* hEX INVERTER 74LS04 Hex Inverter definition
Contextual Info: 04 C O N N E C T IO N D IA G R A M S P IN O U T A •n *''54/7404 O 'n i> & ¡'54H/74H04 ; ■■ ^ 4 S /7 4 S 0 4 / " O /5 4 S /7 4 S 0 4 A ^ 4 L S /7 4 L S 0 4 G 3 E Œ Œ [I Œ d , - /- HEX INVERTER PKGS OUT C O M M E R C IA L G RADE M ILITA R Y G RADE

ST 1076

Abstract: SN74LS214 LCC4270 SN74LS215
Contextual Info: 54/74 FAMILIES OF COMPATIBLE TTL CIRCUITS PIN A SSIG N M EN TS TO P VIEW S R A N D O M -A C C E SS M E M O R IE S Vç c A D H 207 W OE 1/01 V w of 1/01 1/02 1/03 E D G E -T R IG G E R E D W R IT E C O N T R O L 2 5 6 4 -B IT W O RDS C O M M O N I/O PORTS

74LS04 fan-out

Abstract: 7404PC 74LS04PC 74LS04 pinout 74s04p 74Ls04 fanout 74ls04 hex inverter 74LS04* hEX INVERTER 74LS04P 7404FC
Contextual Info: 04 CO NNECTIO N DIAGRAMS PINOUT A ^ 4 /7 4 0 4 ¡54H/74H04 ^ 4S /7 4 S 0 4 /54S/74S04A ^4LS/74LS04 / r Œ Œ [I Œ - 6 3 HEX INVERTER g n d ORDERING CODE: See Section 9 PIN PKGS OUT COMMERCIAL GRADE MILITARY GRADE Vcc = +5.0 V ±5%, T a = 0°C to +70° C

16 bit comparator 74ls

Abstract: 8bit counter 74ls successive approximation 54LS502DM 54LS502FM 74LS502FC 74LS502PC 74LS502
Contextual Info: 502 CO NNECTIO N DIAGRAM PINOUT A {(Q^ 54LS /74LS 502 8-B IT SUCCESSIVE APPR O XIM ATIO N REGISTER DESCRIPTION — The ’LS502 is an 8-bit register w ith the interstage logic necessary to perform serial-to-parallel conversion and provide an active LOW Conversion Com plete (CC signal coincident with storage of the eighth

Contextual Info: 54LS/74LS299 LOGIC SYMBOL DESCRIPTION FEATURES The "299" Is an 8-Bit Bidirectional Universal S h ift/S to ra g e R e g iste r w ith a 3 -sta te bidirectional Input/Output port. The register has four operating modes: shift right, shift left, parallel load, and hold do nothing . The

74165PC

Abstract: 74165 truth table 74LS165PC 74165DC 74LS165 74ls165d 7416 74165 54165DM 54165FM
Contextual Info: 165 C O NNECTIO N DIAGRAM P IN O U T A .« i/7 4 1 6 5 S 5 4 L S /7 4 L S 1 6 5 ' 0 ' / s / ^ * 3 7 8-B IT PAR ALLEL-TO -SER IAL CONVERTER 1 DESCRIPTION — Th e ’ 165 is a n 8 -b it pa ra lle l load or se ria l-in re g is te r w ith c o m p le m e n ta ry o u tp u ts a va ila b le fro m th e last stage. Parallel in p u tin g o c c u rs

74LS138PC

Abstract: 74LS138P 54S138DM 74S138PC demultiplexer 3 to 8 truth table 74LS138 connection for 74LS138 demultiplexer 74ls 74S138DC 74S138
Contextual Info: 138 C O N N E C T IO N D IA G R A M P IN O U T A 54S/74S138 ^ r 54LS/74LS138 &I&C n G c-s> Ao 1-OF-8 DECODER/DEMULTIPLEXER • • • • S C H O T T K Y P R O C E SS FO R H IG H SPEED D E M U L T IP L E X IN G C A P A B ILIT Y M U LT IP L E IN P U T ENABLE FO R EASY EXPANSIO N

54LS378DM

Abstract: 54LS378FM 74LS378DC 74LS378FC 74LS378PC 6bit register
Contextual Info: 378 C O N N E C T IO N D IA G R A M P IN O U T A / / • b ^ V 54LS/74LS378 P A R A L LE L D REGISTER \ With Enable 1 TjOvcc iE QoE Ï Do [3 Ü lD s s ]Q 5 D i[4 là ] 04 Q i[| T 2I Q d2 [| îï] “3 0 2 |T ÏÔ ]0 3 GNO [ T J }C P D E S C R IP T IO N — T h e ’378 is a 6 -b it reg iste r w ith a b u ffe re d co m m o n enable.

OF IC 74170

Abstract: 54170FM
Contextual Info: 170 CO NNECTIO N DIAGRAM PINOUT A 1/54/74170 54LS /74LS 170 11 0 / , ~i ^ T— r 4 X 4 REGISTER FILE With O pen-Collector Outputs DE S C R IP TIO N — The ’170 contains 16 high speed, low power, transparent D-type latches arranged as four words of fou r bits each, to fun ctio n as a

Contextual Info: 74LS256 Signetics Latch Dual 4-Bit Addressable Latch Product Specification Logic Products FEATURES TYPE • Com bines dual dem ultiplexer and 8-bit latch TYPICAL PROPAGATION DELAY TYPICAL SUPPLY CURRENT TOTAL 19ns 22m A 7 4LS 256 • Serial-to-parallel capability

54170DM

Abstract: 54170FM 54LS170DM 74170DC 74170FC 74170PC 74LS170DC 74LS170FC 74LS170PC
Contextual Info: 170 C O N N E C T IO N D IA G R A M P IN O U T A / 1Ì54/74170 ^ <J5 4 L S / 7 4 L S 1 70 0 / , - 7 4 X 4 REGI STER FILE W ith O p e n -C o lle cto r O utputs d2|j d3|7 «Jo, d 4 [3 Ï 4 ] WAo R A i [4 751w a i rao — D E S C R IP T IO N T h e '170 c o n ta in s 16 h igh speed, low p o w e r, tra n sp a re n t

74ls219

Abstract: 74LS189A 54LS219A ls189 74LS219A lta 601 ic 319A SN74LS189A
Contextual Info: SN54LS189A, SN54LS219A, SN54LS289A, SN54LS319A SN74LS189A, SN74LS219A, SN74LS289A, SN74LS319A 64-BIT RANDQM-ACCESS MEMORIES D 2 4 1 7 . SEPTEMBER 1 9 8 0 - REVISED FEBRUARY 1 9 8 5 Organized as 16 Words of Four Bits Each S N 5 4 L S 1 8 9 A . S N 5 4 L S 2 8 9 A . . . J PACKA GE

Contextual Info: SN54LS31, SN74LS31 DELAY ELEMENTS DECEMBER 1983-REVISED MARCH 198B • D elay Elem ents fo r Generating Delay Lines • Inverting and N on-inverting Elements • SN54LS31 J OR W PACKAGE SN74LS31 . . . D OR N PACKAGE TOP VIEW ^ 1 6 3 vcc : 1YC 2 15 D 6 A

LS689

Abstract: d2617 16D06 LS688 SN54LS682 SN54LS689 SN74LS689 sn74ls682
Contextual Info: TYPES SN54LS682 THRU SN54LS689, SN74LS682THRU SN74LS689 8-BIT MAGNITUDE/IDENTITY COMPARATORS D2617, JANUARY 1981-REVJSED DECEMBER 1983 Compares T w o 8-B it Words Choice o f Totem -Pole or Open-Collector Outputs S N 5 4 L S 6 8 2 TH R U S N 5 4 L S 6 8 5 . . . J PACKAGE

74ls189 ram

Abstract: 74LS189 74LS189 logic diagram 74LS189DC 54LS189DM 74LS189PC ls189 54S189DM 74LS189FC 74S189DC
Contextual Info: 189 C O N N E C T IO N D IA G R A M P IN O U T A ¡4S/74S189 l54L S/74L S189 b / / 7 S ö 6 4 -B IT R A N D O M A C C E S S M EM O R Y With 3-S tate O utputs a 0[T 16] V cc c s |X H A, WE j T î7 | A2 Di [ 7 i l ] A3 öl [7 T 2I d 4 d2 ï T|04 [b To] d 3

74LS503DC

Abstract: 74LS503 LS503 2503 successive approximation 54LS503DM 54LS503FM 74LS503FC 74LS503PC
Contextual Info: 503 C O N N E C T IO N D IA G R A M PIN O U T A 54LS/74LS503 8-BIT SUCCESSIVE APPROXIMATION REGISTER With Expansion Control D E S C R IP T IO N — T he ’LS503 re g iste r is_basically th e sam e a s th e ’LS502 ex­ c e p t th a t it has an active LO W Enable (E) in p u t th a t is used in ca sca d in g tw o

1N3064

Abstract: 1N916 74LS 74LS363 N74LS363N
Contextual Info: Signelics 74LS363 L a tc h Octal Transparent Latch With 3-State Outputs Product Specification Logic Products FEATURES • 8-bit transparent latch • 3-state MOS compatible output buffers • Common Latch Enable input with hysteresis • Common 3-state Output Enable

74LS251N

Abstract: multiplexers 74 LS 150 54LS251J
Contextual Info: R C H I I - D S E M IC O N D U C T O R tm DM74LS251 3-STATE Data Selectors/Multiplexers General Description Features These data selectors/m ultiplexers contain full on-chip binary decoding to select one-of-eight d ata sources, and feature a strobe-controlled 3-STATE output. The strobe m ust be at a

Contextual Info: 74LS377 S ignetics Flip-Flop Octal D Flip-Flop With Clock Enable Product Specification Logic Products FEATURES • Ideal for addressable register applications • Clock Enable for address and data synchronization applications • Eight edge-triggered D flip-flops

Contextual Info: I R C H I L D S E M IC O N D U C T O R T M DM74LS251 3-STATE Data Selectors/Multiplexers Features • 3-STATE version o f LS151 To m inim ize the possibility th a t tw o outputs will a ttem pt to take a com m on bus to opposite logic levels, th e output con­