74ACT280 Search Results

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker V cc"4 Type Features: • B uffered inputs u Typical propagation delay: 10 ns @ V Cc = 5 V, T, = 25°C, CL = 50 pF GND- 7 FUNCTIONAL DIAGRAM The RCA CD54/74AC280 and CD54/74ACT280 9 -b it o d d /

cd74ac280

Abstract: 74ac280
Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker £ EVEN X ODD Type Features: NC« 3 3 ZCS- 3 M VCC "14 • B uttered inputs ■ Typical propagation delay: 10 ns @ Vtx - 5 V, T„ = 25°C, C l = 50 pF 6 NO* ? FUNCTIONAL DIAGRAM

74ac280

Contextual Info: T e c h n ic a l D a la - . . CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker X CVCN t 01» NC.3 Vç ç 9 2 CS-5M H » 4 ONO» T Type Features: • Buffered inputs m Typical propagation delay: 10 ns @ Vcc = 5 V, U = 25° C, C l = 50 pF FUNCTIONAL DIAGRAM

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: Technical Data _ CD54/74AC280 CD54/74ACT280 9-Bit Odd/Even Parity Generator/Checker I EVEN Z ODD NC* 3 VCC -14 GNO* 7 »¿fcs-'WH Type Features: • Buffered inputs m Typical propagation delay: 1 0 n s @ Vcc = 5 V, rA= 25° C, CL= 50 pF FUNCTIONAL DIAGRAM

Contextual Info: 74ACT280 9 BIT PARITY GENERATOR/CHECKER . HIGH SPEED: tpD =4 ns TYP. at Vcc =5V • LOW POWER DISSIPATION: Icc = 4 |oA (MAX.) at T a = 25 °C ■ COMPATIBLE WITH TTL OUTPUTS V ih = 2V (MIN), V il = 0.8V(MAX) . 50i2 TRANSMISSION LINE DRIVING CAPABILITY . SYMMETRICAL OUTPUT IMPEDANCE:

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

74ACT280MTR

Abstract: 74ACT280TTR TSSOP14 74ACT280 74ACT280B 74ACT280M
Contextual Info: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), VIL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING

Contextual Info: HD74AC280/74ACT280 • 9-Bit Parity Generator/Checker Description Pin Assignment T he HD74A C 280/H D 74ACT280 is a high-speed p arity generator/checker th a t accepts nine bits o f in p u t d ata and detects w hether an even o r an odd num ber o f these inputs is High. If an even num ber

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

AC280

Abstract: CD54AC280F3A CD54ACT280F3A CD74AC280E CD74AC280M CD74ACT280E
Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

TTL 74-series IC

Abstract: 74ACT280 74ACT280B 74ACT280M AC280
Contextual Info: 74ACT280  9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 4 ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4 µA (MAX.) at TA = 25 oC COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN), VIL = 0.8V (MAX) 50Ω TRANSMISSION LINE DRIVING

74ACT280

Abstract: 74ACT280B 74ACT280M 74ACT280MTR 74ACT280TTR TSSOP14
Contextual Info: 74ACT280 9 BIT PARITY GENERATOR/CHECKER • ■ ■ ■ ■ ■ ■ ■ ■ HIGH SPEED: tPD = 7ns TYP. at VCC = 5V LOW POWER DISSIPATION: ICC = 4µA(MAX.) at TA=25°C COMPATIBLE WITH TTL OUTPUTS VIH = 2V (MIN.), V IL = 0.8V (MAX.) 50Ω TRANSMISSION LINE DRIVING

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity

Contextual Info: CD54/74AC280, CD54/74ACT280 Data sheet acquired from Harris Semiconductor SCHS250A 9-Bit Odd/Even Parity Generator/Checker August 1998 - Revised May 2000 Features data inputs is HIGH. Odd parity is indicated ∑O output is HIGH when an odd number of data inputs is HIGH. Parity