741 IC Search Results

Contextual Info: HMC129 &iS!>5i| MICROWAVE CORPORATION GaAs MMIC DOUBLE-BALANCED MIXER 4 - 8 GHz FE B R U A R Y 1998 Features General Description CONVERSION LOSS: 10dB The H M C129 chip is a miniature double­ LO TO RF AND IF ISOLATION: > 3 0 d B balanced mixer which can be used as an

Contextual Info: H Y 5 1 4 4 0 0 A • H Y U N D A I S e r ie s 1Mx 4-bit CMOS DRAM DESCRIPTION The HY514400A is the 2nd generation and fast dynamic RAM organized 1,048,576 x 4-bit. The HY514400A utilizes Hyundai’s CMOS silicon gate process technology as well as advanced circuit techniques to provide wide operating

Contextual Info: irrtet, VE28F008 8 MBIT 1 MBIT x 8 FLASH MEMORY • High-Denslty Symmetrically Blocked Architecture — Sixteen 64 Kbyte Blocks Very High-Performance Read — 95 ns Maximum Access Time ■ Avionics Temperature Range 40°C to + 125°C Hardware Data Protection Feature

Contextual Info: HIGH-SPEED 16Kx 16 DUAL-PORT STATIC RAM IDT7026S/L Integrated D e vic e Techn olo gy, Inc. multiplexed bus compatibility IDT7026 easily expands data bus width to 32 bits or more using the Master/Slave select when cascading more than one device M/S = H for B U S Y output flag on Master,

Contextual Info: M82510 ASYNCHRONOUS SERIAL CONTROLLER Military • MCS -51 9-Bit Protocol Support ■ ■ Control Character Recognition ■ Asynchronous Operation — 5- to 9-Bit Character Format — Baud Rate DC to 288k — Complete Error Detection ■ CHMOS III with Power Down Mode

XC90

Abstract: intel 82358
Contextual Info: 82355 BUS MASTER INTERFACE CONTROLLER BMIC • Designed for use in 32-Bit EISA Bus Master Expansion Board Designs — Integrates Three interfaces (EISA, Local CPU, and Transfer Buffer) ■ Supports 16- and 32-Bit Burst Transfers — 33 Mbytes/Sec Maximum Data