74 XOR GATE Search Results

1048E

Abstract: 1048E-50 0127A 1048C
Contextual Info: ispLSI 1048E In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

ISPLSI 2096VE-135LTN128I

Abstract: 2096VE-100LT 2096VE 2192VE
Contextual Info: LeadFree a P ckage Options Available! 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect

1048C

Abstract: 1048E
Contextual Info: ispLSI 1048E High-Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Twelve Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

2096VE100LT128

Abstract: 2096VE 2192VE
Contextual Info: ispLSI 2096VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: Larg e 2 0 A rith m e tic S eries 16X 4, 16A 4 Large 20 Arithmetic Series OUTPUTS PRODUCT TERMS ARRAY INPUTS PAL16X4 PAL16A4 COMBINATORIAL REGISTERED 4 4 4 4 16 16 Description The PAL16X4 and PAL16A4 have arithmetic gated feedback. These are specialized devices for arithmetic applications.

1032E

Contextual Info: ispLSI and pLSI 1032E ® High-Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

2192VE

Abstract: 2192VE-135LB144 1NCS R1 2096VE
Contextual Info: ispLSI 2192VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine or Twelve Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

2096VE

Abstract: TQFP 128pin
Contextual Info: ispLSI 2192VL Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic

2096VE

Contextual Info: ispLSI 2192VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

2096VE

Abstract: 2096VL
Contextual Info: ispLSI 2096VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: ® ispLSI and pLSI 2096 High Density Programmable Logic Features Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs 96 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

2096VE

Abstract: 2192VE
Contextual Info: ispLSI 2096VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

2096VE

Contextual Info: ispLSI 2192VL 2.5V In-System Programmable SuperFAST High Density PLD Functional Block Diagram — — — — — 8000 PLD Gates 96 I/O Pins, Nine Dedicated Inputs 192 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State

2096VE

Abstract: 2096VL 20041a
Contextual Info: ispLSI 2096VL Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc.

NT952E,128PIN

Abstract: 128-PIN PQFP
Contextual Info: LeadFree Package Options Available! ispLSI 2096/A In-System Programmable High Density PLD Features Functional Block Diagram • ENHANCEMENTS Output Routing Pool ORP — — — — — 4000 PLD Gates 96 I/O Pins, Six Dedicated Inputs 96 Registers High Speed Global Interconnect

Contextual Info: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

2096VE

Abstract: 2192VE
Contextual Info: ispLSI 2096VE 3.3V In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SuperFAST HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: ispLSI 2096V 3.3V High Density Programmable Logic Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

Contextual Info: ispLSI 2096V 3.3V High-Density Programmable Logic Functional Block Diagram • HIGH-DENSITY PROGRAMMABLE LOGIC — 4000 PLD Gates — 96 I/O Pins, Six Dedicated Inputs — 96 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State

1048C

Abstract: 1048E 1048EA isplsi1048c 1048EA100LT128
Contextual Info: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

R1C390

Abstract: 1048e 100lq128 1048C 1048E 1048EA
Contextual Info: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

100LQ128

Abstract: 1048C 1048E 1048EA
Contextual Info: ispLSI 1048EA In-System Programmable High Density PLD Functional Block Diagram • HIGH DENSITY PROGRAMMABLE LOGIC — 8,000 PLD Gates — 96 I/O Pins, Eight Dedicated Inputs — 288 Registers — High-Speed Global Interconnects — Wide Input Gating for Fast Counters, State

Contextual Info: lattice ispLSI and pLSI 1032E Semiconductor Corporation High-Density Programmable Logic Features Functional Block Diagram ’ HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect

Contextual Info: Lattice' ispLSI and pLSI 1032E | Semiconductor I Corporation High-Density Programmable Logic Functional Block Diagram Features • HIGH DENSITY PROGRAMMABLE LOGIC — 6000 PLD Gates — 64 I/O Pins, Eight Dedicated Inputs — 192 Registers — High Speed Global Interconnect