64BYTE Search Results

Contextual Info: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose

DS4510

Abstract: DS4510U-10 DS4510U-15 DS4510U-5 J-STD-020A
Contextual Info: Rev 1; 6/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose

DS4510U-5

Abstract: J-STD-020A DS4510 DS4510U-10 DS4510U-15
Contextual Info: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose

usop-10

Contextual Info: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I 2 C interface using either fastmode (400kbps) or standard-mode (100kbps) communication. The I/O pins can be used as general-purpose

Contextual Info: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I2C interface using either fast-mode

transistor f8

Abstract: DS4510 DS4510U-10 DS4510U-15 DS4510U-5 J-STD-020A
Contextual Info: Rev 2; 8/04 CPU Supervisor with Nonvolatile Memory and Programmable I/O The DS4510 is a CPU supervisor with integrated 64byte EEPROM memory and four programmable, nonvolatile NV I/O pins. It is configured with an industry-standard I2C interface using either fast-mode

Contextual Info: New Product Highlights TL16C750 Extended FIFO Asynchronous Communications Element I Description The TL16C750 performs parallel-to-serial and serial-to parallel conversion on data characters transmitted to and from the CPU. The ’750 features a 64-byte FIFO, in

TMS34061FNL

Abstract: lad1-5v TMS34070NL S3406 TL 413 SPVU001 MJ340 TA2625
Contextual Info: SM J 3 4 0 1 0 GRAPHICS SYSTEM PROCESSOR NOVEMBER 1 98 8 - • Military Temperature . . . - 5 5 ° C to 12 5°C • Instruction Cycle Time: 200 ns . . . S M J3 4010-40 160 ns . . . S M J3 4010-50 REVISED SEPTEMBER 1989 GB PACKAGE 68-PIN GRID ARRAY TOP VIEW

mip 291

Abstract: mip 290
Contextual Info: SMJ320C80 DIGITAL SIGNAL PROCESSOR SGUS025 – AUGUST 1998 D D D D D D D D D D D D D Single-Chip Parallel Multiple Instruction / Multiple Data MIMD Digital Signal Processor (DSP) More Than Two Billion RISC-Equivalent Operations per Second Master Processor (MP)

Contextual Info: TOSHIBA Original CMOS 8-Bit Microcontroller TLCS-870/C Series TMP86FM25FG Semiconductor Company TMP86FM25 Document Change Notification The purpose of this notification is to inform customers about the launch of the Pb-free version of the device. The introduction of a Pb-free replacement affects the datasheet. Please understand that this

TXC07900AIBG

Abstract: TXC-07900AIBG TSOP transmitter B020H OED155TM TXC-07900-MB VTXP-6 AU-AIS dk12b EK117
Contextual Info: OED155 Device Dual STM-1 Overhead Terminator, Tributary Processor and Cross-Connect with Integrated E1 Mapper TXC-07900 PRODUCT PREVIEW DATA SHEET DESCRIPTION: ™ The Optimized Edge Device, OED155, is a dual STM-1 SDH framer and overhead terminator, virtual tributary

TranSwitch Corporation

Abstract: B2M1-5
Contextual Info: PHAST-1 Device SONET STS-1 Overhead Terminator TXC-06101 DATA SHEET • Provides SONET interface to any type of payload • Programmable STS-1 or STS-N modes • Receive bit-serial STS-1 signal input to the Line Side using external reference frame pulse for

DF2-A

Abstract: XB2H DF2E
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte wide drop and add buses

Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 DESCRIPTION • Maps up to three independent DS3/E3 line formats into SDH/SONET formats as follows: - DS3 to/from STM-1/TUG-3 - DS3 to/from STS-3/STS-1 - E3 to/from STM-1/TUG-3 • SDH/SONET bus access: - Byte-wide drop and add buses

Y446

Abstract: Y443 y441 POP-12 B1 Y447 Y442
Contextual Info: POP-12 Device OC-12 SONET/SDH Path Overhead Processor, Retimer, and Cross Connect TXC-06603 DATA SHEET PRODUCT PREVIEW DESCRIPTION • Path overhead POH processing for up to 12 x STS-1 SPEs or 4 x VC-4/STS-3c SPEs • 4 Tx and 4 Rx Pointer Tracking State Machines

GR-1400

Contextual Info: PHAST-12E Device Programmable, High-Performance ATM/PPP/TDM SONET/SDH Terminator for Level 12 with Enhanced Features TXC-06212 TECHNICAL OVERVIEW LINE SIDE Serial LIU Clocks The PHAST-12E is a highly integrated SONET/SDH terminator device designed for ATM cell, frame, higher order multiplexing,

TH4B

Contextual Info: PHAST-3N STM-1/STS-3/STS-3c SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06103 DATA SHEET • • • • • • • • • • • • • • • • • Bit-serial SDH/SONET line interface - Pseudo-ECL interface with clock recovery and synthesis

TUG-3

Abstract: vc-4 digital cross connect
Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453B TECHNICAL OVERVIEW Each of the three channels of the TL3M can map a DS3 line signal into an STM-1 TUG-3 or STS-3 STS-1 SPE SDH/SONET signal. An E3 signal can be mapped only into an STM-1 TUG-3. The TL3M interfaces to an STM-1 or STS-3 SDH/SONET signal

A1515-1

Contextual Info: EtherMap -48 Device OC-48 SONET/SDH Ethernet Mapper TXC-06710 TECHNICAL OVERVIEW PRODUCT PREVIEW TERMINAL SIDE Control & Clock EEPROM Signals Serial Interface EtherMap™-48 TXC-06710 is a highly-integrated device for mapping IEEE 802.3 100/1000 Mbps Ethernet and block encoded

Contextual Info: TL3M Device Triple Level 3 Mapper TXC-03453 TECHNICAL OVERVIEW SDH/SONET SIDE TELECOM BUS O-Bit Interfaces • Add/drop multiplexers • Digital cross connect systems • Broadband switching systems • Transmission equipment External Alarm Interfaces Drop Bus

Contextual Info: Sertopia Device UTOPIA Serializer TXC-05860 DATA SHEET PRODUCT PREVIEW The Sertopia™ TXC-05860 UTOPIA serializer is a single-chip solution for broadband communication systems. A pair of Sertopia devices interface two remote UTOPIA ports transparently across a serial link. The Sertopia emulates a

MC 4011 BCP

Abstract: PKT 4113 API ncp 6131 SWITCHING SYSTEMS INTERNATIONAL sqm 225 leach 1522 her 4541 MSP SNCP t 1451 n 52 toh SWITCHING SYSTEMS INTERNATIONAL sqm 350 k2400 EQUIVALENT
Contextual Info: EtherPHAST -24 Device 2x OC-12/STM-4 SONET/SDH Ethernet Mapper TXC-06745 DATA SHEET TXC-06745-MB, Ed. 2 February 2006 FEATURES APPLICATIONS • Client Interfaces: 2x GMII/24x SMII/4x TBI/MPI 24 channel packet all pin shared • Two serial Gigabit Ethernet (1.25 Gbit/s) ports with integrated CRSU/SerDes (8B/10B)

Contextual Info: PHAST -12N Device STM-4/OC-12 SDH/SONET Overhead Terminator with Telecom Bus Interface TXC-06312 DESCRIPTION • Bit-serial LVPECL SDH/SONET line interface with integrated clock recovery and clock synthesis - single 622.08 Mbit/s STM-4/OC-12 signal or - four 155.52 Mbit/s STM-1/OC-3 signals

Contextual Info: NRND: Not recommended for new designs. TE X AS I NS TRUM E NTS - P RO DUCTION D ATA Stellaris LM3S1B21 Microcontroller D ATA SHE E T D S -LM3S 1B 21 - 1 3 4 4 2 . 2 5 4 9 S P M S 222H C o p yri g h t 2 0 07-2012 Te xa s In stru me n ts In co rporated